Rowhammer and Disturb Effects: Debug Playbook

Debug playbook

Debug Playbook for Rowhammer and Disturb Effects focuses on hammer threshold margin, disturb-induced bit flip count, mitigation hit rate. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

DRAM debug should narrow from broad symptom to one dominant mechanism. Avoid mixed-knob sweeps that produce accidental wins without causal confidence.

1. Freeze workload seed, firmware image, timing profile, and thermal setup.

2. Find first failing transition in command timeline.

3. Classify mechanism: locality loss, legality pressure, queue policy, margin drift, or RAS behavior.

4. Build focused reproducer for top hypothesis.

5. Apply minimal reversible fix and define rollback gate.

6. Re-run full performance + reliability matrix.

Debug decision tree

ROOT CAUSE TREE - Rowhammer and Disturb Effects

hammer threshold margin, disturb-induced bit flip count, mitigation hit rate regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Review memo template

DRAM REVIEW MEMO - Reliability, ECC & Security / Rowhammer and Disturb Effects

1. Symptom
   - Watched metric: hammer threshold margin, disturb-induced bit flip count, mitigation hit rate
   - Failing traffic slice: <workload/phase/class>
   - First failing transition: <row-hit/row-conflict/turnaround/refresh/training>
   - Revision tags: <firmware/controller/timing/board/package>

2. Mechanism hypothesis
   - Primary mechanism: High-frequency activation of aggressor rows injects disturbance into adjacent victim rows, causing data corruption unless mitigated with TRR policies, refresh adaptation, mapping randomization, and controller throttling.
   - Competing hypotheses: <mapping, scheduling, PHY margin, SI/PI, reliability policy>
   - Missing evidence: <command trace, queue snapshot, lane margins, CE/UE logs>

3. Proposed action
   - Smallest reversible change: <policy/register/firmware/flow>
   - Expected movement: <p99 latency, effective bandwidth, stability>
   - Regression risk: fairness, thermal drift, training robustness, field reliability

4. Signoff
   - Re-run artifact: rowhammer stress log, aggressor-victim address trace, mitigation counter report
   - Required owners: memory controller owner, security architect, validation owner
   - Final decision: ship, bounded rollout, rollback, or escalate

DRAM deep dive

Reliability closure combines ECC policy, scrub cadence, and disturbance mitigation like row-hammer controls.

Concept diagram

RELIABILITY LOOP

error detect -> ECC correct/report -> scrub/retire policy -> monitor recurrence

Metric graph

ERROR MANAGEMENT TREND

correctable events    ███████
silent-data-risk      ██
unrecoverable events  █

Reports and artifacts

• correctable/uncorrectable error trend

• scrub interval effectiveness report

• row-hammer monitor log

• fault-injection coverage summary

Mini case study

Relaxed scrub interval improved bandwidth in test but allowed burst correctables to cluster into service-visible latency spikes.

Debug branches

• Segment ECC events by bank, rank, and temperature

• Tune scrub cadence with workload-aware idle windows

• Verify row-hammer mitigation using adversarial patterns

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Principal DRAM review addendum

Rowhammer and Disturb Effects should be read as an end-to-end memory behavior, not as a single block definition. A production DRAM subsystem reflects interactions between array physics, command legality, scheduler policy, PHY margin, and reliability controls before software experiences final latency or bandwidth.

High-frequency activation of aggressor rows injects disturbance into adjacent victim rows, causing data corruption unless mitigated with TRR policies, refresh adaptation, mapping randomization, and controller throttling. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use hammer threshold margin, disturb-induced bit flip count, mitigation hit rate as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as rowhammer stress log, aggressor-victim address trace, mitigation counter report.

Reliability closure requires combining ECC telemetry, disturb mitigation, and thermal policy into one operating contract. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

Review discipline should enforce a single causal chain: traffic pattern -> command-level behavior -> array/PHY effect -> measured product impact. That chain prevents tuning folklore from replacing evidence.