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Course contents

  • How to Use This Course
  • SoC Integration Metrics Reference
  • SoC Integration Glossary
  • Reading Path
  • Hierarchy & Budget Contracts61
  • Clock & Reset Architecture61
  • Bus Fabrics & Interconnect61
    • NoC Topology & QoS
    • AXI/ACE Contracts
    • Coherency & Ordering Integration
      • Coherency & Ordering Integration: Mechanism
      • Coherency & Ordering Integration: Inputs & Outputs
      • Coherency & Ordering Integration: Reports & Metrics
      • Coherency & Ordering Integration: Debug Playbook
      • Coherency & Ordering Integration: Worked Example
      • Coherency & Ordering Integration: Pitfalls & Red Flags
      • Coherency & Ordering Integration: Interview Drills
      • Coherency & Ordering Integration: Review Checklist
      • Coherency & Ordering Integration: Theory Deep Dive
      • Coherency & Ordering Integration: Design Space
      • Coherency & Ordering Integration: Expanded Case Study
      • Coherency & Ordering Integration: Step-by-Step Walkthrough
      • Coherency & Ordering Integration: Comparison Matrix
      • Coherency & Ordering Integration: Software / Programmer View
      • Coherency & Ordering Integration: Silicon PPA Impact
    • Fabric Contention Debug
    • Bus Fabrics & Interconnect: Tricky Q&A
  • Memory Maps & I/O61
  • IP Integration & Handoff61
  • Package & Interface61
  • Chip-Level Signoff61
  • SoC Interview Prep4
  • SoC Integration Cheatsheet
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‹Coherency & Ordering Integration
  1. Topics
  2. SoC Design
  3. Bus Fabrics & Interconnect
  4. Coherency & Ordering Integration
  5. Coherency & Ordering Integration: Comparison Matrix

SoC Integration · All levels

Coherency & Ordering Integration: Comparison Matrix

Comparison Matrix for Coherency & Ordering Integration.

On this page

    Comparison matrix

    NoC/AXI policy choices trade fairness, throughput, and determinism.

    Diagram
    +------------------+----------------+----------------+----------------+
    | Approach         | Strength       | Weakness       | Best when      |
    +------------------+----------------+----------------+----------------+
    | Strict           | predictable    | slower early   | new program    |
    | Balanced         | practical      | needs rigor    | stable teams   |
    | Aggressive       | fast           | escape risk    | late schedule  |
    | Re-architect     | durable        | expensive      | recurring failures |
    +------------------+----------------+----------------+----------------+

    When to choose each approach

    • Pick the approach based on residual silicon risk, not only schedule pressure.

    Review traps

    • Policy-only arguments without artifact evidence

    • Unbounded waivers

    Evidence comparison

    Diagram
    INTEGRATION EVIDENCE MATRIX — Coherency & Ordering Integration
    
    +-------------------+------------------------+--------------------------+-------------------------+
    | Evidence           | Tells you              | Does not prove           | Next action             |
    +-------------------+------------------------+--------------------------+-------------------------+
    | Manifest diff      | baseline changed       | root cause itself        | isolate first delta     |
    | Domain trace       | where behavior diverged| ownership accountability | map to contract owner   |
    | Signoff dashboard  | closure posture        | reproducibility quality  | verify source artifacts |
    | Bring-up logs       | software-visible symptom| physical/timing cause   | correlate with HW trace |
    | Waiver register    | accepted residual risk | technical closure        | review expiry criteria  |
    +-------------------+------------------------+--------------------------+-------------------------+

    SoC deep dive

    Fabric correctness and contention behavior must be proven together.

    Concept diagram

    Diagram
    FABRIC FLOW
    masters -> routers/VCs -> slaves + memory

    Metric graph

    Diagram
    LATENCY TAIL
    p50 ███
    p95 ██████
    p99 ██████████

    Reports and artifacts

    • NoC contention heatmap

    • ordering violation report

    • QoS fairness summary

    • protocol trace

    Mini case study

    Bandwidth looked fine at average load, but p99 tail violated SLA due to arbitration starvation.

    Debug branches

    • Isolate traffic class

    • Check ordering assumptions

    • Audit arbitration policy

    Senior review question

    Ask: what baseline, owner, and artifact prove this topic is truly closed?

    Key takeaways

    • State baseline manifest and owner with every closure metric.

    • Run cross-domain regression after every top-level fix.

    Common pitfalls

    • Comparing results across different manifests.

    • Unowned issues slipping through review cycles.

    • Waiving risks without expiry and validation plan.

    Principal SoC review addendum

    Coherency correctness requires consistent shareability, home-node behavior, and ordering barriers across CPU, DMA, and accelerator masters.

    Metric: stale-data escapes, coherency retry rate, fence latency

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    See also

    • Coherency & Ordering Integration: Mechanism
    • Coherency & Ordering Integration: Inputs & Outputs
    • Coherency & Ordering Integration: Reports & Metrics