Interview Drills for Coherency & Ordering Integration focuses on stale-data escapes, coherency retry rate, fence latency. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.
PROMPT
You observe stale-data escapes, coherency retry rate, fence latency in Coherency & Ordering Integration. Explain root cause and closure plan.
STRONG ANSWER
1. Names baseline manifest and failing boundary.
2. Explains Coherency correctness requires consistent shareability, home-node behavior, and ordering barriers across CPU, DMA, and accelerator masters.
3. Requests coherency litmus logs, line-state timeline, ordering matrix.
4. Proposes minimal reversible fix + full regression scope.
WEAK ANSWER
Suggests broad optimizations or owner blame without baseline and artifact evidence.COHERENCY FLOW
core write -> line state transition -> snoop/invalidate -> observer read
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ordering barrier
Barrier bugs appear as stale-data escapes, not obvious protocol errors.ROOT-CAUSE TREE — Coherency & Ordering Integration
stale-data escapes, coherency retry rate, fence latency regressed
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same baseline manifest?
/ \
no yes
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version/collateral real integration
mismatch contract break
/ \ |
inputs env isolate domain
drift drift and first failureFabric correctness and contention behavior must be proven together.
FABRIC FLOW
masters -> routers/VCs -> slaves + memoryLATENCY TAIL
p50 ███
p95 ██████
p99 ██████████NoC contention heatmap
ordering violation report
QoS fairness summary
protocol trace
Bandwidth looked fine at average load, but p99 tail violated SLA due to arbitration starvation.
Isolate traffic class
Check ordering assumptions
Audit arbitration policy
Ask: what baseline, owner, and artifact prove this topic is truly closed?
State baseline manifest and owner with every closure metric.
Run cross-domain regression after every top-level fix.
Comparing results across different manifests.
Unowned issues slipping through review cycles.
Waiving risks without expiry and validation plan.
Coherency correctness requires consistent shareability, home-node behavior, and ordering barriers across CPU, DMA, and accelerator masters.
Metric: stale-data escapes, coherency retry rate, fence latency
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