Debug playbook

Debug Playbook for Coherency & Ordering Integration focuses on stale-data escapes, coherency retry rate, fence latency. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

Integration debug is a search for the first contract break, not the loudest downstream failure signature.

Root-cause tree

ROOT-CAUSE TREE — Coherency & Ordering Integration

stale-data escapes, coherency retry rate, fence latency regressed
         |
   same baseline manifest?
      /           \
    no             yes
    |               |
version/collateral  real integration
mismatch            contract break
 /       \            |
inputs    env      isolate domain
drift     drift    and first failure

1. Freeze baseline manifest and owner matrix.

2. Find first failing boundary and earliest reproducible symptom.

3. Classify failure type: contract, collateral, implementation, or governance.

4. Prove with one reduced experiment.

5. Apply smallest owner-controlled fix.

6. Run focused verification and full cross-domain regression.

Review memo template

STAFF SOC REVIEW MEMO — Bus Fabrics & Interconnect / Coherency & Ordering Integration

1. Symptom
   - Watched metric: stale-data escapes, coherency retry rate, fence latency
   - Failing integration boundary: <domain/interface>
   - Baseline manifest: <hash/tag>
   - Repro setup: <sim/emulation/fpga/silicon + fw tag>

2. Mechanism hypothesis
   - Primary mechanism: Coherency correctness requires consistent shareability, home-node behavior, and ordering barriers across CPU, DMA, and accelerator masters.
   - Competing hypothesis: <contract drift, collateral mismatch, implementation bug, governance gap>
   - Missing evidence: <trace, report, checklist, signoff artifact>

3. Proposed action
   - Minimal reversible fix: <contract update, config patch, RTL fix, process guardrail>
   - Expected metric movement: <delta and scope>
   - Regression risk: timing, power, functionality, schedule

4. Signoff
   - Re-run artifact: coherency litmus logs, line-state timeline, ordering matrix
   - Required owners: system architect, cache owner, verification lead
   - Final decision: close, waive (bounded), or escalate

SoC deep dive

Fabric correctness and contention behavior must be proven together.

Concept diagram

FABRIC FLOW
masters -> routers/VCs -> slaves + memory

Metric graph

LATENCY TAIL
p50 ███
p95 ██████
p99 ██████████

Reports and artifacts

• NoC contention heatmap

• ordering violation report

• QoS fairness summary

• protocol trace

Mini case study

Bandwidth looked fine at average load, but p99 tail violated SLA due to arbitration starvation.

Debug branches

• Isolate traffic class

• Check ordering assumptions

• Audit arbitration policy

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Coherency correctness requires consistent shareability, home-node behavior, and ordering barriers across CPU, DMA, and accelerator masters.

Metric: stale-data escapes, coherency retry rate, fence latency