Hardware / software view

Master behavior and ordering semantics drive integration correctness.

What firmware teams feel

• Boot instability

• Contract drift after minor RTL change

Contract impact

• Register defaults

• interrupt behavior

• clock/reset assumptions

Build and integration notes

• Synth/PD assumptions can invalidate software expectations

Mitigations

• Versioned contracts

• joint hw/sw readiness reviews

HW/SW CONTRACT — Coherency & Ordering Integration
// firmware init order must match reset/clock release assumptions

Layer software touches

SOC INTEGRATION LAYERS — Coherency & Ordering Integration

layer               owns                          failure mode
-----------------   ---------------------------   ------------------------
architecture        partition + contracts         impossible budgets
ip handoff          models + collateral           integration mismatch
fabric/clock/reset  global behavior               domain deadlock
physical/package    route + SI/PI + IO            late closure churn
signoff process     manifests + waivers           non-reproducible claims
program governance  owners + escalations          schedule collapse

SoC deep dive

Fabric correctness and contention behavior must be proven together.

Concept diagram

FABRIC FLOW
masters -> routers/VCs -> slaves + memory

Metric graph

LATENCY TAIL
p50 ███
p95 ██████
p99 ██████████

Reports and artifacts

• NoC contention heatmap

• ordering violation report

• QoS fairness summary

• protocol trace

Mini case study

Bandwidth looked fine at average load, but p99 tail violated SLA due to arbitration starvation.

Debug branches

• Isolate traffic class

• Check ordering assumptions

• Audit arbitration policy

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Coherency correctness requires consistent shareability, home-node behavior, and ordering barriers across CPU, DMA, and accelerator masters.

Metric: stale-data escapes, coherency retry rate, fence latency