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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
    • The Integrator Role and Handoffs
      • What the Integrator Owns
      • Anatomy of a Handoff
      • NanoSoC Cast and First Triage
    • Spec to Tapeout Flow
    • Contracts and Ownership
    • Reading the SoC Spec
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←The Integrator Role and Handoffs
  1. Topics
  2. SoC Design
  3. What SoC Integration Is
  4. The Integrator Role and Handoffs
  5. What the Integrator Owns
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    Part 1 of 14, lesson 1 of 12Part 1 of 14/What SoC Integration Is/Lesson 1 of 12All levels

    What the Integrator Owns

    The integrator's five duties, drawn against block owners, architects, verification, PD and software.

    Why it matters

    On NanoSoC bring-up day the DMA interrupt never fires, although the DMA status register reads DONE equals 1 and the interrupt pin at the block is high. The block owner proves the DMA is correct: its irq output is indeed high, exactly as its register map promises. The software team proves the driver is correct: it enabled the right bit. Both are right and the chip is still broken, because the wire between them lands on controller input 6, a spare, instead of input 1. Nobody's block is wrong; the integration is wrong. That gap, everything true of each part but false of the whole, is the integrator's territory.

    The core idea

    Six parties touch the chip and each owns a different truth. The architect owns the structure: partitions, the address map skeleton, clock and power domains, and the budgets each block must meet. The block owner owns one block's behaviour against its specification, with collateral to prove it. Verification owns the proof that the assembled chip does what the specification says, at block, subsystem and chip level. Physical design owns turning the netlist into geometry that closes timing and power. Software owns the drivers and images built against the hardware-software contract. The integrator owns what falls between them: the top-level wiring, the map, the decode, the crossing inventory, the reset and power sequences, the version of every shared table, and the proof that every handoff into the chip is complete.

    Five duties make that concrete. First, own the shared tables: the address map, the interrupt map, the clock and reset lists, the power-state table, the pin map. Second, own the top-level structure: the interconnect configuration, the bridges, the decoders, the default slaves, the tie-offs. Third, own handoff acceptance: no block enters the chip without its collateral, checked, versioned and stamped. Fourth, own the sequences: reset release order, power-up and power-down order, clock enable order, boot order. Fifth, own the change: when any table moves, every consumer is regenerated and rechecked before the change lands.

    Symptom on NanoSoC

    Block view

    Integration view (the integrator's fix)

    DMA irq high, controller RAW bit 1 is 0, bit 6 is 1

    DMA correct; controller correct

    Wire moved to input 1; connectivity test per source

    Write to SBR CTRL corrupts the next DMA word

    Both blocks correct alone

    Slot decode overlap; one source map generating the decoder

    Second DMA job uses the stale KEY with no error

    DMA behaves as specified

    Driver rule and contract review: LEN and KEY need BUSY equals 0 first

    Chip wakes immediately after entering SLEEP

    Power controller correct alone

    Two missing isolation clamps on interrupt lines; UPF crossing check

    SBR read of secure SRAM errors on the first beat

    Memory and bridge correct alone

    Master security attribute left at reset default; per-master attribute table

    The table above is worth reading twice, because it is the whole course in miniature: each row names a real NanoSoC failure from the ten planted bugs of the course, shows both sides passing their own checks, and gives the integration-level fix. The integrator's skill is recognising the third column from the first, routing it to the right owner, and installing the check that catches the class next time.

    What the review looks for

    • Every shared table names one owner and one version; no table has two editors.

    • Every symptom has a routing: the triage table for the area exists before the bug arrives.

    • Block-level passing is never accepted as chip-level proof; the integration checks have their own sign-off line.

    Verify and debug

    When a symptom arrives, reproduce it at the top level first, then split the difference: force the source and observe the sink, as the third lesson does with the interrupt table. If the source is right and the sink is right, the defect is in the contract between them, which belongs to the integrator. Resist the reflex to open the block RTL; the fastest evidence is usually a connectivity or table check, not a waveform inside a block that already passes its own tests.

    Interrupt numbering off by an offset: the wiring uses the hardware input number while the software table counts from a different base, so the handler for the wrong device runs. On NanoSoC the DMA is input 1; a driver table that counts from 1 enables the SBR line instead. Both sides pass alone. The cure is integrator-owned: one table generating the RTL tie-offs, the software header and a per-source interrupt test.

    If asked what an integrator does all day, answer with the five duties, then offer the interrupt story: two correct blocks, one wrong wire, and the per-source connectivity test that now guards it.

    Check yourself The architect and the integrator disagree about who decides the address map. Who is right?

    Both, split by phase: the architect sets the skeleton and the budgets, the integrator owns the versioned table, generates every consumer from it, and says no to moves once software depends on it.

    Related topics

    • Next: Anatomy of a Handoff

    • Contracts and Ownership

    • Hardware Debug: The Cost of a Bug by Stage

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    See also

    • NanoSoC Cast and First Triage