A processor that cannot be interrupted on time is a liability, and a DMA engine that moves data nobody ordered is worse. This section is the integrator's view of both: how eight interrupt lines travel from their sources through synchronisers and a controller into the CPU, how the NanoSoC DMA and its stream bridge move blocks between the SRAM banks under software control, how the UART, SPI and GPIO hang off a slow peripheral bus, and how sixteen GPIO pads, shared with the UART and SPI signals, are muxed so that each peripheral pad follows its enable bit. Every latency, baud rate and register offset is a NanoSoC reference value, and every lesson names the review check that proves the wiring right.
Topic | What it covers | After it you can... |
|---|---|---|
Level versus edge, polarity, fixed priority, masking, the 8-input NanoSoC controller and its wiring review | Wire any active-high level source into the controller, program masks and the TOP register, and review an interrupt table. | |
The DMA irq path across isolation and two synchronisers, best and worst latency, spurious and lost interrupts | Bound the irq-to-CPU latency in nanoseconds, and diagnose a missed, doubled or stuck interrupt. | |
The NanoSoC streaming DMA and stream bridge: register sequence, contract quirks, length agreement, throughput, clock gating | Program a DMA job that completes with DONE and a single irq, and explain every way the contract can surprise a driver. | |
UART, SPI and GPIO as integrated blocks: register maps, clocks, resets, interrupts, bridges and bring-up order | Bring the slow peripherals up in the right order and predict the cost of every register access. | |
The 31-pad NanoSoC pad model: which GPIO pads UART and SPI share and how the EN bits select them, reset states and pulls, ball-out and simultaneous switching | Write a pin-mux table with no conflicts, set safe reset defaults, and check the pad count and the switching limit. |
Suggested order: top to bottom. The controller must make sense before its routing latency can be bounded; the DMA lessons assume the interrupt path already works, because DMA completion is signalled by interrupt; the peripherals reuse the same bus, clock and reset ideas; and pad muxing closes the section at the package boundary. Readers chasing one bug can start at its topic: a stuck irq at the second, a corrupt DMA buffer at the third, a silent UART at the fourth, a contended pin at the fifth. For the generic delivery models see Interrupts and Notification; for the DMA mechanism itself see The DMA You Will Verify.
All three are integration-owned glue between blocks and software: none of them computes anything, but each decides whether events and data arrive at all, on time, and at the right destination. The integrator owns the tables, the timing and the review for all three.