The NanoSoC DMA is the UVM course's streaming engine dropped into a real memory system: it has no memory port of its own, only an AXI-Stream input and output, so a new stream bridge feeds it from SRAM and drains it back. This topic teaches the DMA as the integrator owns it: the exact register sequence that starts a job, the four contract quirks that trap every first driver, the length agreement between the two blocks that must both say 64, and the clock gate that can hang the bus if software is careless. For the DMA mechanism itself see The DMA You Will Verify; for descriptor-based relatives see Descriptors, Rings and Doorbells.
Lesson | After it you can... |
|---|---|
Start a job, poll or take its interrupt, and clear it without tripping any quirk. | |
Program the bridge, keep both LEN registers equal, and price any transfer. | |
Read the completion waveform and gate the DMA clock without hanging the bus. |
Suggested order: top to bottom. The register contract first, because every later lesson programs it; then the bridge that makes the stream engine useful; then completion and gating, which is where the interrupt of the previous topic meets the data path. The peripheral topic next door (Peripheral Subsystem) reuses the same APB access costs quoted here.
The DMA moves AXI-Stream words to AXI-Stream words and has no memory master. Something must read SRAM into its input stream and write its output stream back to SRAM; that something is the bridge, which is the only AXI master besides the CPU.