The fast part of NanoSoC moves megabytes; the slow part moves characters, configuration bits and single pins, and the chip cannot boot without it. The UART prints the first banner, the SPI loads the second-stage image, and the GPIO gives software sixteen pins to read and drive. NanoSoC has no boot straps: it has one boot source, the SPI flash. This topic integrates all three as finished blocks on the slow APB segment: what their registers do, what each access costs in nanoseconds, how their interrupts and resets are wired, and the order software brings them up. For the peripheral protocols themselves see Embedded Peripherals; for the block-level shell see Peripheral Shell.
Lesson | After it you can... |
|---|---|
Set the baud rate, budget the overrun window, and wire the UART interrupt. | |
Load an image over SPI and configure GPIO direction and interrupts safely. | |
Price every peripheral access and bring the subsystem up in the right order. |
Suggested order: top to bottom. The UART first because its deadline is the tightest; then SPI and GPIO, which share the segment and the reset story; then the bridges and the bring-up order that both depend on. Pad wiring for the GPIO pins continues in Pad Muxing and GPIO.
They run on clk_per at 24 MHz with the always-on logic, so they stay alive in sleep while the 96 MHz fabric sleeps. The crossing costs about 208 ns per access, which character traffic never notices.