Interface Protocols · All levels

Embedded Peripherals (I2C / SPI / UART)

Low-speed serial protocol timing, arbitration, chip-select behavior, FIFOs, DMA hooks, interrupts, and driver-visible contracts.

Section goal

Low-speed serial protocol timing, arbitration, chip-select behavior, FIFOs, DMA hooks, interrupts, and driver-visible contracts.

How to study this section

Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.

Topics

i2c-timing-and-arbitration/ — I2C Timing & Arbitration
spi-modes-and-cs-rules/ — SPI Modes & Chip-Select Rules
uart-flow-control/ — UART Flow Control
peripheral-integration-debug/ — Peripheral Integration Debug

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

diagram

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

NACK rate
overrun count
CS setup/hold violations
IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

If overrun, FIFO depth vs ISR latency vs DMA burst.
If NACK on I2C, pull-ups, speed, and clock stretch.
If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Practice this lesson

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