PROMPT
You see frame error rate, chip-select timing violation, throughput on SPI Modes & Chip-Select Rules. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains SPI relies on CPOL/CPHA, chip-select timing, shift order, and device-specific framing agreements.
3. Requests MOSI/MISO/SCLK/CS waveform, mode table, device timing spec.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

SPI MODES

Mode | CPOL | CPHA | sample edge
-----+------+------+-------------
  0  |  0   |  0   | rising
  1  |  0   |  1   | falling
  2  |  1   |  0   | falling
  3  |  1   |  1   | rising

WAVE (Mode 0):
CS   ‾‾\____________________/‾‾
SCLK ____|‾|_|‾|_|‾|_|‾|________
MOSI    D7  D6  D5  D4
        ^ sampled on rising edge

ROOT-CAUSE TREE — SPI Modes & Chip-Select Rules

frame error rate, chip-select timing violation, throughput looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time