PCIe transaction, data-link, and physical layers; enumeration; link training; credits; CXL attach modes; and performance tuning.
Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.
pcie-layering-and-tlp/ — PCIe Layering & TLPs
enumeration-and-link-training/ — Enumeration & Link Training
cxl-attach-modes/ — CXL Attach Modes
pcie-cxl-debug/ — PCIe / CXL Debug
PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.
PCIe DEBUG TOP-DOWN
L0 link healthy? -> credits OK? -> TLP completes? -> driver happy?
Skip a layer and you will mis-own the bug.LINK DEGRADE EXAMPLE
target x4 Gen4 ---- ---- ---- ----
actual x4 Gen4 ---- ---- ---- ---- (eval board)
actual x1 Gen3 - (product board)
Package/SI often shows up as width downgrade, not hard fail.link width/speed
replay count
completion timeout
AER error log
LTSSM history
Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.
If degrade at width/speed, PHY/SI before driver.
If replay storm, link layer before transaction layer.
If CXL coherency bug, separate .io vs .cache vs .mem traffic.
Ask: what is the first transaction that deviates, and which spec rule does it test?