PCIe & CXL

Section goal

PCIe transaction, data-link, and physical layers; enumeration; link training; credits; CXL attach modes; and performance tuning.

How to study this section

1. Start with the topic hub to learn the contract.

2. Use mechanism and reports pages to connect rules to metrics.

3. Use debug and worked-example pages for interview and on-call practice.

4. Close with checklist and PPA impact before signing any change.

Topics

1. pcie-layering-and-tlp/ — PCIe Layering & TLPs

2. enumeration-and-link-training/ — Enumeration & Link Training

3. cxl-attach-modes/ — CXL Attach Modes

4. pcie-cxl-debug/ — PCIe / CXL Debug

Related topics

• Protocols course hub

Protocol deep dive

PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.

Concept diagram

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Metric graph

LINK DEGRADE EXAMPLE

target x4 Gen4  ---- ---- ---- ----
actual   x4 Gen4  ---- ---- ---- ----   (eval board)
actual   x1 Gen3  -                   (product board)

Package/SI often shows up as width downgrade, not hard fail.

Metrics and artifacts to collect

• link width/speed

• replay count

• completion timeout

• AER error log

• LTSSM history

Mini case study

Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.

Debug branches

• If degrade at width/speed, PHY/SI before driver.

• If replay storm, link layer before transaction layer.

• If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?