Interface Protocols · All levels

AMBA Family (APB / AHB / AXI)

APB register access, AHB bursts, AXI channels, AXI-Lite, AXI-Stream, bridges, interconnect, and integration pitfalls.

Section goal

APB register access, AHB bursts, AXI channels, AXI-Lite, AXI-Stream, bridges, interconnect, and integration pitfalls.

How to study this section

Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.

Topics

apb-ahb-basics/ — APB & AHB Basics
axi-channels-and-transfers/ — AXI Channels & Transfers
axi-lite-and-axi-stream/ — AXI-Lite & AXI-Stream
amba-integration-debug/ — AMBA Integration Debug

Protocol deep dive

AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

Concept diagram

diagram

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Metric graph

diagram

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

Metrics and artifacts to collect

AR/AW/R/B channel utilization
write resp latency
read OSTD depth
SLVERR/DECERR count
bridge hang log

Mini case study

Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

Debug branches

Hung write: verify AW/W ordering and wlast alignment.
Hung read: check arready stall and rlast per ID.
Decode errors: address map vs interconnect route table.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Practice this lesson

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