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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
    • APB & AHB Basics
    • AXI Channels & Transfers
    • AXI-Lite & AXI-Stream
      • AXI-Lite & AXI-Stream: Mechanism
      • AXI-Lite & AXI-Stream: Inputs & Outputs
      • AXI-Lite & AXI-Stream: Reports & Metrics
      • AXI-Lite & AXI-Stream: Debug Playbook
      • AXI-Lite & AXI-Stream: Worked Example
      • AXI-Lite & AXI-Stream: Pitfalls & Red Flags
      • AXI-Lite & AXI-Stream: Interview Drills
      • AXI-Lite & AXI-Stream: Review Checklist
      • AXI-Lite & AXI-Stream: Theory Deep Dive
      • AXI-Lite & AXI-Stream: Design Space
      • AXI-Lite & AXI-Stream: Expanded Case Study
      • AXI-Lite & AXI-Stream: Step-by-Step Walkthrough
      • AXI-Lite & AXI-Stream: Comparison Matrix
      • AXI-Lite & AXI-Stream: Software / Programmer View
      • AXI-Lite & AXI-Stream: Silicon PPA Impact
    • AMBA Integration Debug
    • AMBA Family (APB / AHB / AXI): Tricky Q&A
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹AXI-Lite & AXI-Stream
  1. Topics
  2. Bus Protocols
  3. AMBA Family (APB / AHB / AXI)
  4. AXI-Lite & AXI-Stream
  5. AXI-Lite & AXI-Stream: Reports & Metrics

Interface Protocols · All levels

AXI-Lite & AXI-Stream: Reports & Metrics

Reports & Metrics for AXI-Lite & AXI-Stream.

On this page

    Reports and metrics

    Reports & Metrics for AXI-Lite & AXI-Stream focuses on register response latency, stream bubble rate, packet boundary errors. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    The job of a report is to turn register response latency, stream bubble rate, packet boundary errors into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.

    Metric movement

    Diagram
    METRIC GRAPH — register response latency, stream bubble rate, packet boundary errors
    
    throughput / success
      ^
      |                         target
      |                       - - - - - - -
      |                  o after bounded fix
      |              o
      |         o baseline
      |    o failing run
      +--------------------------------------> experiment
        config A     isolated root cause     accepted change
    
    Readout:
      - compare identical payload, clock, reset, traffic seed, and firmware setup
      - separate headline bandwidth from useful payload bandwidth
      - explain why the protocol mechanism moved the metric

    Latency distribution

    Diagram
    LATENCY HISTOGRAM — AXI-Lite & AXI-Stream
    
    count
      |               ███
      |             ███████
      |          █████████████
      |        █████████████████        <- long tail = the real complaint
      |      ████████████████████████████
      +------------------------------------> latency
       p50      p90    p95       p99  (watch p99, not the average)
    
    Average hides the tail; product pain lives at p95/p99.
    • Track register response latency, stream bubble rate, packet boundary errors by traffic class, payload size, and clock/reset mode.

    • Report p50/p95/p99 latency when user-visible stalls matter.

    • Include legal maximums and product targets; they are not the same thing.

    • Always store the metric next to the artifact that produced it.

    Protocol deep dive

    AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

    Concept diagram

    Diagram
    AMBA INTEGRATION MAP
    
    CPU --AXI--> NIC --AXI--> SRAM
      |              |
      +--AXI-Lite--> peripherals (GPIO, timers)
      +--AXI-Stream-> video pipe
    
    Every bridge is a contract rewrite: width, ID, burst, cache attrs.

    Metric graph

    Diagram
    AXI CHANNEL ACTIVITY (mixed traffic)
    
    AW+W     ████████████
    AR       ████████████████
    R        ██████████████
    B        ████████
    
    Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

    Metrics and artifacts to collect

    • AR/AW/R/B channel utilization

    • write resp latency

    • read OSTD depth

    • SLVERR/DECERR count

    • bridge hang log

    Mini case study

    Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

    Debug branches

    • Hung write: verify AW/W ordering and wlast alignment.

    • Hung read: check arready stall and rlast per ID.

    • Decode errors: address map vs interconnect route table.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    How to read the numbers

    register response latency, stream bubble rate, packet boundary errors must be split by traffic class, payload size, and reset mode.

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    See also

    • AXI-Lite & AXI-Stream: Mechanism
    • AXI-Lite & AXI-Stream: Worked Example
    • AXI-Lite & AXI-Stream: Pitfalls & Red Flags