AXI-Lite & AXI-Stream: Interview Drills

PROMPT
You see register response latency, stream bubble rate, packet boundary errors on AXI-Lite & AXI-Stream. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains AXI-Lite removes bursts for control paths while AXI-Stream moves ordered data without addresses.
3. Requests TVALID/TREADY trace, TLAST packet log, control register access test.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

AXI-STREAM PACKET

clk     _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
tvalid  _|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____
tready  _|‾‾‾‾‾|__|‾‾‾‾‾‾‾‾‾|_____   (consumer backpressure mid-packet)
tdata    B0  B1  --  B2  B3
tlast    ________________|‾|_____   (marks end of packet)

Bubble: when tready=0, the same beat is held; data must not change.

ROOT-CAUSE TREE — AXI-Lite & AXI-Stream

register response latency, stream bubble rate, packet boundary errors looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.