AXI-Lite & AXI-Stream: Mechanism

Mechanism to understand

Mechanism for AXI-Lite & AXI-Stream focuses on register response latency, stream bubble rate, packet boundary errors. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

AXI-Lite removes bursts for control paths while AXI-Stream moves ordered data without addresses. Think of it as a contract enforced at boundaries: the sender promises stability and legality, the receiver promises forward progress, and the fabric in between promises not to silently change identity or ordering.

• Identify the transaction boundary: request, data, response, completion, or retry.

• Identify the flow-control boundary: valid/ready, grant, credit, FIFO depth, or lane state.

• Identify what the receiver is allowed to assume and what the sender must hold stable.

Layered view

PROTOCOL STACK VIEW — AXI-Lite & AXI-Stream

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

AXI-Stream packet with TLAST

AXI-STREAM PACKET

clk     _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
tvalid  _|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____
tready  _|‾‾‾‾‾|__|‾‾‾‾‾‾‾‾‾|_____   (consumer backpressure mid-packet)
tdata    B0  B1  --  B2  B3
tlast    ________________|‾|_____   (marks end of packet)

Bubble: when tready=0, the same beat is held; data must not change.

AXI-Lite vs AXI-Full

AXI-LITE vs AXI-FULL

AXI-Lite : single beat, no burst, no ID reorder  -> control/registers
AXI-Full : bursts, IDs, reorder, outstanding      -> data movement

Use Lite for a register block; do not pay for burst logic you never use.

Layer responsibilities

LAYER RESPONSIBILITY — AXI-Lite & AXI-Stream

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

Concept diagram

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Metric graph

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

Metrics and artifacts to collect

• AR/AW/R/B channel utilization

• write resp latency

• read OSTD depth

• SLVERR/DECERR count

• bridge hang log

Mini case study

Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

Debug branches

• Hung write: verify AW/W ordering and wlast alignment.

• Hung read: check arready stall and rlast per ID.

• Decode errors: address map vs interconnect route table.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Mechanism deep dive

AXI-Lite removes bursts for control paths while AXI-Stream moves ordered data without addresses.

Walk the transaction forward: request accepted → data moves → response completes → software visible effect.