DenseChip

Interface Protocols · All levels

AMBA Family (APB / AHB / AXI): Tricky Q&A

Senior interview and review questions for AMBA Family (APB / AHB / AXI).

Section Q&A bank

Use these drills after completing all topics in AMBA Family (APB / AHB / AXI). Answer with layer, transaction, metric, artifact, and regression.

Why does AXI split reads and writes into separate channels?

diagram
[INT][PROT][AMBA-FAMILY]

Q: Why does AXI split reads and writes into separate channels?

A:
So address, data, and response for reads and writes can progress independently, improving throughput under latency.

FOLLOW-UP TRAP: Describing AXI as a single shared bus.

What must match between AW and W for a write burst?

diagram
[INT][PROT][AMBA-FAMILY]

Q: What must match between AW and W for a write burst?

A:
Burst length, size, ID, and address alignment; W beats must follow AW rules.

FOLLOW-UP TRAP: Checking only the first W beat.

When is AXI-Lite preferred over full AXI?

diagram
[INT][PROT][AMBA-FAMILY]

Q: When is AXI-Lite preferred over full AXI?

A:
Simple register access without bursts or reorder — control paths and small peripherals.

FOLLOW-UP TRAP: Using Lite for DMA traffic.

Where do bridge bugs usually hide?

diagram
[INT][PROT][AMBA-FAMILY]

Q: Where do bridge bugs usually hide?

A:
ID remap, width conversion, burst splitting, cache attribute propagation, and ordering.

FOLLOW-UP TRAP: Blaming the endpoint master only.

Q&A drill guide

diagram
LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSION

Sketch while answering

diagram
AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Common traps

  • Hung write: verify AW/W ordering and wlast alignment.

  • Hung read: check arready stall and rlast per ID.

  • Decode errors: address map vs interconnect route table.

Key takeaways

  • Connect every protocol claim to a transaction identity and measurable metric.

  • Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

  • Debugging timeouts without finding the first bad transaction.

  • Quoting peak bus width without payload efficiency and retry overhead.

  • Treating VIP compliance as a substitute for system integration replay.

Practice this lesson