Interface Protocols · All levels

Protocol Fundamentals

Layering, transaction models, handshake semantics, ordering, backpressure, clock domains, and bandwidth/latency budgeting.

Section goal

Layering, transaction models, handshake semantics, ordering, backpressure, clock domains, and bandwidth/latency budgeting.

How to study this section

  1. Start with the topic hub to learn the contract.

  2. Use mechanism and reports pages to connect rules to metrics.

  3. Use debug and worked-example pages for interview and on-call practice.

  4. Close with checklist and PPA impact before signing any change.

Topics

  1. layering-and-transaction-model/ — Layering & Transaction Model

  2. handshake-and-backpressure/ — Handshake & Backpressure

  3. ordering-and-outstanding-rules/ — Ordering & Outstanding Rules

  4. bandwidth-latency-budgeting/ — Bandwidth & Latency Budgeting

Related topics

Protocol deep dive

Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

Concept diagram

diagram
FUNDAMENTALS STACK

software intent
     |
transaction (ID, addr, len, attr, order)
     |
link/channel (handshake, credit, retry)
     |
physical (clock, reset, lanes, PHY)

Debug golden rule: never change layers without carrying transaction identity.

Metric graph

diagram
STALL BREAKDOWN EXAMPLE

ready stalls      ████████████████  42%
credit wait       ██████████        26%
ordering block    ██████            16%
reset/config      ████              10%
other             ██                6%

If ready stalls dominate, widening the bus will not help.

Metrics and artifacts to collect

  • transaction latency by class

  • ready stall cycles

  • outstanding depth utilization

  • payload efficiency vs headline width

  • retry and error rate

Mini case study

A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

Debug branches

  • If latency spikes but bandwidth flat, check outstanding limits and ordering.

  • If throughput collapses at high load, draw the knee curve — you are past queue stability.

  • If intermittent, compare reset release order and clock domain boundaries.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?