Layering, transaction models, handshake semantics, ordering, backpressure, clock domains, and bandwidth/latency budgeting.
Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.
layering-and-transaction-model/ — Layering & Transaction Model
handshake-and-backpressure/ — Handshake & Backpressure
ordering-and-outstanding-rules/ — Ordering & Outstanding Rules
bandwidth-latency-budgeting/ — Bandwidth & Latency Budgeting
Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.
FUNDAMENTALS STACK
software intent
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transaction (ID, addr, len, attr, order)
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link/channel (handshake, credit, retry)
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physical (clock, reset, lanes, PHY)
Debug golden rule: never change layers without carrying transaction identity.STALL BREAKDOWN EXAMPLE
ready stalls ████████████████ 42%
credit wait ██████████ 26%
ordering block ██████ 16%
reset/config ████ 10%
other ██ 6%
If ready stalls dominate, widening the bus will not help.transaction latency by class
ready stall cycles
outstanding depth utilization
payload efficiency vs headline width
retry and error rate
A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.
If latency spikes but bandwidth flat, check outstanding limits and ordering.
If throughput collapses at high load, draw the knee curve — you are past queue stability.
If intermittent, compare reset release order and clock domain boundaries.
Ask: what is the first transaction that deviates, and which spec rule does it test?