Reports & Metrics for Handshake & Backpressure focuses on ready deassertion rate, queue occupancy, throughput collapse point. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.
The job of a report is to turn ready deassertion rate, queue occupancy, throughput collapse point into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.
METRIC GRAPH — ready deassertion rate, queue occupancy, throughput collapse point
throughput / success
^
| target
| - - - - - - -
| o after bounded fix
| o
| o baseline
| o failing run
+--------------------------------------> experiment
config A isolated root cause accepted change
Readout:
- compare identical payload, clock, reset, traffic seed, and firmware setup
- separate headline bandwidth from useful payload bandwidth
- explain why the protocol mechanism moved the metricLATENCY HISTOGRAM — Handshake & Backpressure
count
| ███
| ███████
| █████████████
| █████████████████ <- long tail = the real complaint
| ████████████████████████████
+------------------------------------> latency
p50 p90 p95 p99 (watch p99, not the average)
Average hides the tail; product pain lives at p95/p99.Track ready deassertion rate, queue occupancy, throughput collapse point by traffic class, payload size, and clock/reset mode.
Report p50/p95/p99 latency when user-visible stalls matter.
Include legal maximums and product targets; they are not the same thing.
Always store the metric next to the artifact that produced it.
Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.
FUNDAMENTALS STACK
software intent
|
transaction (ID, addr, len, attr, order)
|
link/channel (handshake, credit, retry)
|
physical (clock, reset, lanes, PHY)
Debug golden rule: never change layers without carrying transaction identity.STALL BREAKDOWN EXAMPLE
ready stalls ████████████████ 42%
credit wait ██████████ 26%
ordering block ██████ 16%
reset/config ████ 10%
other ██ 6%
If ready stalls dominate, widening the bus will not help.transaction latency by class
ready stall cycles
outstanding depth utilization
payload efficiency vs headline width
retry and error rate
A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.
If latency spikes but bandwidth flat, check outstanding limits and ordering.
If throughput collapses at high load, draw the knee curve — you are past queue stability.
If intermittent, compare reset release order and clock domain boundaries.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
ready deassertion rate, queue occupancy, throughput collapse point must be split by traffic class, payload size, and reset mode.
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