Handshake & Backpressure

What this topic teaches

Handshake & Backpressure is about converting a protocol rule into a measurable silicon contract. valid/ready, request/grant, and credit schemes move pressure upstream before buffers overflow. The hard part is never the happy-path diagram; it is proving, under real traffic, which layer and which transaction broke the contract.

The senior-engineer question

When ready deassertion rate, queue occupancy, throughput collapse point moves, can you identify the transaction, the protocol layer, the responsible owner, and the smallest experiment that proves the root cause?

PROTOCOL STACK VIEW — Handshake & Backpressure

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

Picture the protocol

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

VALID/READY handshake waveform

VALID / READY HANDSHAKE (transfer happens when both are high)

clk     _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
valid   ____|‾‾‾‾‾‾‾‾‾‾‾|________
ready   ________|‾‾‾‾‾‾‾|____________
xfer              ^   ^
                  |   |
       transfer on cycles where valid & ready are both 1

Read rule:
  - valid must NOT wait for ready (no combinational deadlock)
  - data must stay stable while valid is high and ready is low

Backpressure propagation

BACKPRESSURE TRAVELS UPSTREAM

producer --valid--> [FIFO] --valid--> consumer
         <--ready--        <--ready--

consumer slow  -> FIFO fills -> ready deasserts -> producer stalls

OCCUPANCY GRAPH (FIFO depth over time)
depth
 8 |              ____
 6 |          ___/    \___        <- near-full = ready will drop
 4 |       __/            \__
 2 |  ____/                  \____
 0 +--------------------------------> time
        burst in        drain out

Transaction sequence

SEQUENCE — Handshake & Backpressure

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: ready deassertion rate, queue occupancy, throughput collapse point

Who owns which layer

LAYER RESPONSIBILITY — Handshake & Backpressure

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Evidence to collect

• Primary metric: ready deassertion rate, queue occupancy, throughput collapse point.

• Primary artifact: waveform with stall windows, credit counter trace, FIFO occupancy graph.

• Owners to bring into review: RTL owner, verification owner, performance owner.

• Spec clause or requirement ID for every claim.

• One traffic replay that fails and one reduced sequence that isolates the rule.

Ownership map

OWNERSHIP MAP — Handshake & Backpressure

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        RTL owner
spec/VIP            verification owner
firmware/system     performance owner

Rule: every metric must have a named owner before a review starts.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Carry transaction identity across waveform, log, counter, and spec view.

• Separate protocol violation, integration configuration, and performance bottleneck before proposing a fix.

• Draw the diagram first; the waveform should confirm the picture, not replace it.

Common pitfalls

• Debugging only one channel or layer.

• Treating a VIP error message as root cause instead of evidence.

• Quoting peak interface bandwidth without payload efficiency.

Protocol deep dive

Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

Concept diagram

FUNDAMENTALS STACK

software intent
     |
transaction (ID, addr, len, attr, order)
     |
link/channel (handshake, credit, retry)
     |
physical (clock, reset, lanes, PHY)

Debug golden rule: never change layers without carrying transaction identity.

Metric graph

STALL BREAKDOWN EXAMPLE

ready stalls      ████████████████  42%
credit wait       ██████████        26%
ordering block    ██████            16%
reset/config      ████              10%
other             ██                6%

If ready stalls dominate, widening the bus will not help.

Metrics and artifacts to collect

• transaction latency by class

• ready stall cycles

• outstanding depth utilization

• payload efficiency vs headline width

• retry and error rate

Mini case study

A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

Debug branches

• If latency spikes but bandwidth flat, check outstanding limits and ordering.

• If throughput collapses at high load, draw the knee curve — you are past queue stability.

• If intermittent, compare reset release order and clock domain boundaries.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.