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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
    • Layering & Transaction Model
    • Handshake & Backpressure
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Protocol Fundamentals
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Protocol Fundamentals: Tricky Q&A

Interface Protocols · All levels

Protocol Fundamentals: Tricky Q&A

Senior interview and review questions for Protocol Fundamentals.

On this page

    Section Q&A bank

    Use these drills after completing all topics in Protocol Fundamentals. Answer with layer, transaction, metric, artifact, and regression.

    Why must valid not depend combinationally on ready?

    Diagram
    [INT][PROT][PROTOCOL-FUNDAMENTALS]
    
    Q: Why must valid not depend combinationally on ready?
    
    A:
    It creates a combinational loop between producer and consumer that can deadlock when both wait on each other.
    
    FOLLOW-UP TRAP: Saying 'because the spec says so' without explaining deadlock.

    What is the difference between headline bandwidth and payload efficiency?

    Diagram
    [INT][PROT][PROTOCOL-FUNDAMENTALS]
    
    Q: What is the difference between headline bandwidth and payload efficiency?
    
    A:
    Headline is width×frequency; payload efficiency removes protocol overhead, idle cycles, retries, and turnarounds.
    
    FOLLOW-UP TRAP: Quoting peak GB/s from the datasheet.

    When can transactions with different IDs complete out of order?

    Diagram
    [INT][PROT][PROTOCOL-FUNDAMENTALS]
    
    Q: When can transactions with different IDs complete out of order?
    
    A:
    When the protocol allows reorder across IDs; same-ID ordering rules still apply.
    
    FOLLOW-UP TRAP: Claiming all buses are strictly ordered.

    What is the first artifact you collect when a transaction hangs?

    Diagram
    [INT][PROT][PROTOCOL-FUNDAMENTALS]
    
    Q: What is the first artifact you collect when a transaction hangs?
    
    A:
    Waveform or VIP log showing the first point progress stopped, with ID/address tagged.
    
    FOLLOW-UP TRAP: Increasing timeout or widening the bus.

    Q&A drill guide

    Diagram
    LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSION

    Sketch while answering

    Diagram
    FUNDAMENTALS STACK
    
    software intent
         |
    transaction (ID, addr, len, attr, order)
         |
    link/channel (handshake, credit, retry)
         |
    physical (clock, reset, lanes, PHY)
    
    Debug golden rule: never change layers without carrying transaction identity.

    Common traps

    • If latency spikes but bandwidth flat, check outstanding limits and ordering.

    • If throughput collapses at high load, draw the knee curve — you are past queue stability.

    • If intermittent, compare reset release order and clock domain boundaries.

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    PreviousNext: AMBA Family (APB / AHB / AXI)

    Up next

    Up nextAMBA Family (APB / AHB / AXI)

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    See also

    • Layering & Transaction Model
    • Handshake & Backpressure
    • Ordering & Outstanding Rules