Link bring-up, packet framing, lane training, PHY/digital split, MAC/PCS boundaries, and system-level bandwidth planning.
Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.
usb-link-and-packet-model/ — USB Link & Packet Model
ethernet-mac-phy-basics/ — Ethernet MAC / PHY Basics
mipi-csi-dsi-overview/ — MIPI CSI / DSI Overview
high-speed-io-debug/ — High-Speed I/O Debug
USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.
HIGH-SPEED STACK
app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
CRC errors often mean PCS/PHY/channel, not TCP.BER vs EQ SETTING
BER
1e-3 |*
1e-6 | *
1e-9 | **** usable window
1e-12| *
+-----------------> EQ tapCRC error rate
retrain count
frame drop
lane error
BER
Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.
If link up but lossy, PHY margin and retrain.
If enumeration OK but throughput low, check packet size and DMA batching.
If MIPI frame drops, blanking budget and lane polarity.
Ask: what is the first transaction that deviates, and which spec rule does it test?