High-Speed I/O (USB / Ethernet / MIPI)

Section goal

Link bring-up, packet framing, lane training, PHY/digital split, MAC/PCS boundaries, and system-level bandwidth planning.

How to study this section

1. Start with the topic hub to learn the contract.

2. Use mechanism and reports pages to connect rules to metrics.

3. Use debug and worked-example pages for interview and on-call practice.

4. Close with checklist and PPA impact before signing any change.

Topics

1. usb-link-and-packet-model/ — USB Link & Packet Model

2. ethernet-mac-phy-basics/ — Ethernet MAC / PHY Basics

3. mipi-csi-dsi-overview/ — MIPI CSI / DSI Overview

4. high-speed-io-debug/ — High-Speed I/O Debug

Related topics

• Protocols course hub

Protocol deep dive

USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

Concept diagram

HIGH-SPEED STACK

app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel

CRC errors often mean PCS/PHY/channel, not TCP.

Metric graph

BER vs EQ SETTING

BER
1e-3 |*
1e-6 |  *
1e-9 |     **** usable window
1e-12|          *
     +-----------------> EQ tap

Metrics and artifacts to collect

• CRC error rate

• retrain count

• frame drop

• lane error

• BER

Mini case study

Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

Debug branches

• If link up but lossy, PHY margin and retrain.

• If enumeration OK but throughput low, check packet size and DMA batching.

• If MIPI frame drops, blanking budget and lane polarity.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?