Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
      • High-Speed I/O Debug: Mechanism
      • High-Speed I/O Debug: Inputs & Outputs
      • High-Speed I/O Debug: Reports & Metrics
      • High-Speed I/O Debug: Debug Playbook
      • High-Speed I/O Debug: Worked Example
      • High-Speed I/O Debug: Pitfalls & Red Flags
      • High-Speed I/O Debug: Interview Drills
      • High-Speed I/O Debug: Review Checklist
      • High-Speed I/O Debug: Theory Deep Dive
      • High-Speed I/O Debug: Design Space
      • High-Speed I/O Debug: Expanded Case Study
      • High-Speed I/O Debug: Step-by-Step Walkthrough
      • High-Speed I/O Debug: Comparison Matrix
      • High-Speed I/O Debug: Software / Programmer View
      • High-Speed I/O Debug: Silicon PPA Impact
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
Loading lesson

‹High-Speed I/O Debug
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. High-Speed I/O Debug
  5. High-Speed I/O Debug: Reports & Metrics

Interface Protocols · All levels

High-Speed I/O Debug: Reports & Metrics

Reports & Metrics for High-Speed I/O Debug.

On this page

    Reports and metrics

    Reports & Metrics for High-Speed I/O Debug focuses on BER, link retrain count, throughput under real traffic. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    The job of a report is to turn BER, link retrain count, throughput under real traffic into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.

    Metric movement

    Diagram
    METRIC GRAPH — BER, link retrain count, throughput under real traffic
    
    throughput / success
      ^
      |                         target
      |                       - - - - - - -
      |                  o after bounded fix
      |              o
      |         o baseline
      |    o failing run
      +--------------------------------------> experiment
        config A     isolated root cause     accepted change
    
    Readout:
      - compare identical payload, clock, reset, traffic seed, and firmware setup
      - separate headline bandwidth from useful payload bandwidth
      - explain why the protocol mechanism moved the metric

    Latency distribution

    Diagram
    LATENCY HISTOGRAM — High-Speed I/O Debug
    
    count
      |               ███
      |             ███████
      |          █████████████
      |        █████████████████        <- long tail = the real complaint
      |      ████████████████████████████
      +------------------------------------> latency
       p50      p90    p95       p99  (watch p99, not the average)
    
    Average hides the tail; product pain lives at p95/p99.
    • Track BER, link retrain count, throughput under real traffic by traffic class, payload size, and clock/reset mode.

    • Report p50/p95/p99 latency when user-visible stalls matter.

    • Include legal maximums and product targets; they are not the same thing.

    • Always store the metric next to the artifact that produced it.

    Protocol deep dive

    USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

    Concept diagram

    Diagram
    HIGH-SPEED STACK
    
    app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
    
    CRC errors often mean PCS/PHY/channel, not TCP.

    Metric graph

    Diagram
    BER vs EQ SETTING
    
    BER
    1e-3 |*
    1e-6 |  *
    1e-9 |     **** usable window
    1e-12|          *
         +-----------------> EQ tap

    Metrics and artifacts to collect

    • CRC error rate

    • retrain count

    • frame drop

    • lane error

    • BER

    Mini case study

    Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

    Debug branches

    • If link up but lossy, PHY margin and retrain.

    • If enumeration OK but throughput low, check packet size and DMA batching.

    • If MIPI frame drops, blanking budget and lane polarity.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    How to read the numbers

    BER, link retrain count, throughput under real traffic must be split by traffic class, payload size, and reset mode.

    This content block can't be displayed here.

    Block type: unknown

    This content block can't be displayed here.

    Block type: unknown

    PreviousNext: High-Speed I/O Debug: Debug Playbook

    Up next

    Up nextHigh-Speed I/O Debug: Debug Playbook

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • High-Speed I/O Debug: Mechanism
    • High-Speed I/O Debug: Worked Example
    • High-Speed I/O Debug: Pitfalls & Red Flags