MAC/PCS/PHY split defines where bugs live and which team owns them.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Baseline | known, signed | may miss peak | shipping SKU |
| More buffer | absorbs latency | area, deadlock | DMA-heavy |
| Wider bus | peak BW up | timing, power | memory bound |
| SW contract | cheap silicon | driver burden | fixed platform |
+------------------+----------------+----------------+----------------+Pick baseline when schedule and risk dominate
Pick buffering only after proving backpressure is the limiter
Pick width only after payload efficiency analysis
Pick software contract when hardware change is too expensive
Comparing peak spec numbers across protocols
Ignoring bridge and firmware in the comparison
One-size-fits-all answer in interviews
COMPLIANCE / DEBUG MATRIX — High-Speed I/O Debug
+-------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------+------------------------+--------------------------+-------------------------+
| Waveform | signal-level sequence | full system intent | map to transaction log |
| VIP transaction | spec-level behavior | RTL micro-cause | correlate timestamp |
| Counter / PMU | aggregate symptom | single failing packet | isolate traffic class |
| Firmware log | software-visible flow | electrical/link health | compare with hardware |
| Analyzer capture | external protocol view | internal reset/config | align with RTL trace |
+-------------------+------------------------+--------------------------+-------------------------+USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.
HIGH-SPEED STACK
app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
CRC errors often mean PCS/PHY/channel, not TCP.BER vs EQ SETTING
BER
1e-3 |*
1e-6 | *
1e-9 | **** usable window
1e-12| *
+-----------------> EQ tapCRC error rate
retrain count
frame drop
lane error
BER
Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.
If link up but lossy, PHY margin and retrain.
If enumeration OK but throughput low, check packet size and DMA batching.
If MIPI frame drops, blanking budget and lane polarity.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Re-read High-Speed I/O Debug against one concrete product workload, not a synthetic directed test.
debug crosses digital packet counters, PHY adaptation, board SI, firmware sequencing, and workload traffic shape.
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