Use these drills after completing all topics in High-Speed I/O (USB / Ethernet / MIPI). Answer with layer, transaction, metric, artifact, and regression.
[INT][PROT][HIGH-SPEED-IO]
Q: Link up but high CRC — where to look?
A:
PCS/PHY/SI/channel; digital framing may be fine while electrical margin is not.
FOLLOW-UP TRAP: Rewriting the driver first.[INT][PROT][HIGH-SPEED-IO]
Q: Why does BER have a window vs EQ setting?
A:
Too little EQ leaves ISI; too much amplifies noise; optimal is center of low-BER region.
FOLLOW-UP TRAP: Picking max EQ setting.LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSIONHIGH-SPEED STACK
app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
CRC errors often mean PCS/PHY/channel, not TCP.If link up but lossy, PHY margin and retrain.
If enumeration OK but throughput low, check packet size and DMA batching.
If MIPI frame drops, blanking budget and lane polarity.
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.