Memory Interfaces (DDR / LPDDR / HBM)

Section goal

Controller/PHY split, training, timing modes, refresh, bank conflicts, bandwidth efficiency, and memory subsystem debug.

How to study this section

1. Start with the topic hub to learn the contract.

2. Use mechanism and reports pages to connect rules to metrics.

3. Use debug and worked-example pages for interview and on-call practice.

4. Close with checklist and PPA impact before signing any change.

Topics

1. ddr-controller-phy-split/ — DDR Controller / PHY Split

2. training-and-timing-modes/ — Training & Timing Modes

3. refresh-and-bandwidth-efficiency/ — Refresh & Bandwidth Efficiency

4. memory-interface-debug/ — Memory Interface Debug

Related topics

• Protocols course hub

Protocol deep dive

DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

Concept diagram

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Metric graph

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.

Metrics and artifacts to collect

• effective BW

• row hit rate

• refresh stall %

• training margin

• ECC error log

Mini case study

Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

Debug branches

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?