Controller/PHY split, training, timing modes, refresh, bank conflicts, bandwidth efficiency, and memory subsystem debug.
Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.
ddr-controller-phy-split/ — DDR Controller / PHY Split
training-and-timing-modes/ — Training & Timing Modes
refresh-and-bandwidth-efficiency/ — Refresh & Bandwidth Efficiency
memory-interface-debug/ — Memory Interface Debug
DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.
MEMORY PATH
masters -> controller scheduler -> PHY -> DRAM banks
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refresh/QoS training/margin
Scheduler sees transactions; PHY sees picoseconds.BANDWIDTH LOSS WATERFALL
peak ████████████████████████
refresh █████████████████████
turnaround ██████████████████
row miss ██████████████
effective ██████████████
Quote the bottom bar in reviews.effective BW
row hit rate
refresh stall %
training margin
ECC error log
Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.
If ECC errors, check training margin and address interleave first.
If BW low with high row hit, suspect port arbitration not DRAM.
If boot fail, stop at training step in transcript.
Ask: what is the first transaction that deviates, and which spec rule does it test?