PROMPT
You see training margin, eye width, boot failure rate on Training & Timing Modes. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains training aligns DQS/DQ timing and voltage margins so digital transfers survive PVT and board/package variation.
3. Requests training transcript, margin report, mode register dump.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

READ DATA EYE (sample in the center of the opening)

voltage
  ^      ____________
  |     /            \        <- wider eye = more margin
  |    /   sample     \
  |   |      .         |
  |    \              /
  |     \____________/
  +-------------------------> time (DQS phase)
        ^           ^
     left edge   right edge
   center = (left+right)/2  -> training picks this point

ROOT-CAUSE TREE — Training & Timing Modes

training margin, eye width, boot failure rate looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.