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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
    • DDR Controller / PHY Split
    • Training & Timing Modes
      • Training & Timing Modes: Mechanism
      • Training & Timing Modes: Inputs & Outputs
      • Training & Timing Modes: Reports & Metrics
      • Training & Timing Modes: Debug Playbook
      • Training & Timing Modes: Worked Example
      • Training & Timing Modes: Pitfalls & Red Flags
      • Training & Timing Modes: Interview Drills
      • Training & Timing Modes: Review Checklist
      • Training & Timing Modes: Theory Deep Dive
      • Training & Timing Modes: Design Space
      • Training & Timing Modes: Expanded Case Study
      • Training & Timing Modes: Step-by-Step Walkthrough
      • Training & Timing Modes: Comparison Matrix
      • Training & Timing Modes: Software / Programmer View
      • Training & Timing Modes: Silicon PPA Impact
    • Refresh & Bandwidth Efficiency
    • Memory Interface Debug
    • Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Training & Timing Modes
  1. Topics
  2. Bus Protocols
  3. Memory Interfaces (DDR / LPDDR / HBM)
  4. Training & Timing Modes
  5. Training & Timing Modes: Reports & Metrics

Interface Protocols · All levels

Training & Timing Modes: Reports & Metrics

Reports & Metrics for Training & Timing Modes.

On this page

    Reports and metrics

    Reports & Metrics for Training & Timing Modes focuses on training margin, eye width, boot failure rate. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    The job of a report is to turn training margin, eye width, boot failure rate into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.

    Metric movement

    Diagram
    METRIC GRAPH — training margin, eye width, boot failure rate
    
    throughput / success
      ^
      |                         target
      |                       - - - - - - -
      |                  o after bounded fix
      |              o
      |         o baseline
      |    o failing run
      +--------------------------------------> experiment
        config A     isolated root cause     accepted change
    
    Readout:
      - compare identical payload, clock, reset, traffic seed, and firmware setup
      - separate headline bandwidth from useful payload bandwidth
      - explain why the protocol mechanism moved the metric

    Latency distribution

    Diagram
    LATENCY HISTOGRAM — Training & Timing Modes
    
    count
      |               ███
      |             ███████
      |          █████████████
      |        █████████████████        <- long tail = the real complaint
      |      ████████████████████████████
      +------------------------------------> latency
       p50      p90    p95       p99  (watch p99, not the average)
    
    Average hides the tail; product pain lives at p95/p99.
    • Track training margin, eye width, boot failure rate by traffic class, payload size, and clock/reset mode.

    • Report p50/p95/p99 latency when user-visible stalls matter.

    • Include legal maximums and product targets; they are not the same thing.

    • Always store the metric next to the artifact that produced it.

    Protocol deep dive

    DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

    Concept diagram

    Diagram
    MEMORY PATH
    
    masters -> controller scheduler -> PHY -> DRAM banks
                  |                      |
             refresh/QoS            training/margin
    
    Scheduler sees transactions; PHY sees picoseconds.

    Metric graph

    Diagram
    BANDWIDTH LOSS WATERFALL
    
    peak              ████████████████████████
    refresh           █████████████████████
    turnaround        ██████████████████
    row miss          ██████████████
    effective         ██████████████
    
    Quote the bottom bar in reviews.

    Metrics and artifacts to collect

    • effective BW

    • row hit rate

    • refresh stall %

    • training margin

    • ECC error log

    Mini case study

    Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

    Debug branches

    • If ECC errors, check training margin and address interleave first.

    • If BW low with high row hit, suspect port arbitration not DRAM.

    • If boot fail, stop at training step in transcript.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    How to read the numbers

    training margin, eye width, boot failure rate must be split by traffic class, payload size, and reset mode.

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    See also

    • Training & Timing Modes: Mechanism
    • Training & Timing Modes: Worked Example
    • Training & Timing Modes: Pitfalls & Red Flags