Controller policy, PHY margin, and traffic shape set effective bandwidth.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Baseline | known, signed | may miss peak | shipping SKU |
| More buffer | absorbs latency | area, deadlock | DMA-heavy |
| Wider bus | peak BW up | timing, power | memory bound |
| SW contract | cheap silicon | driver burden | fixed platform |
+------------------+----------------+----------------+----------------+Pick baseline when schedule and risk dominate
Pick buffering only after proving backpressure is the limiter
Pick width only after payload efficiency analysis
Pick software contract when hardware change is too expensive
Comparing peak spec numbers across protocols
Ignoring bridge and firmware in the comparison
One-size-fits-all answer in interviews
COMPLIANCE / DEBUG MATRIX — Training & Timing Modes
+-------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------+------------------------+--------------------------+-------------------------+
| Waveform | signal-level sequence | full system intent | map to transaction log |
| VIP transaction | spec-level behavior | RTL micro-cause | correlate timestamp |
| Counter / PMU | aggregate symptom | single failing packet | isolate traffic class |
| Firmware log | software-visible flow | electrical/link health | compare with hardware |
| Analyzer capture | external protocol view | internal reset/config | align with RTL trace |
+-------------------+------------------------+--------------------------+-------------------------+DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.
MEMORY PATH
masters -> controller scheduler -> PHY -> DRAM banks
| |
refresh/QoS training/margin
Scheduler sees transactions; PHY sees picoseconds.BANDWIDTH LOSS WATERFALL
peak ████████████████████████
refresh █████████████████████
turnaround ██████████████████
row miss ██████████████
effective ██████████████
Quote the bottom bar in reviews.effective BW
row hit rate
refresh stall %
training margin
ECC error log
Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.
If ECC errors, check training margin and address interleave first.
If BW low with high row hit, suspect port arbitration not DRAM.
If boot fail, stop at training step in transcript.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Re-read Training & Timing Modes against one concrete product workload, not a synthetic directed test.
training aligns DQS/DQ timing and voltage margins so digital transfers survive PVT and board/package variation.
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