Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A

Section Q&A bank

Use these drills after completing all topics in Memory Interfaces (DDR / LPDDR / HBM). Answer with layer, transaction, metric, artifact, and regression.

Why is effective DDR bandwidth below peak?

[INT][PROT][MEMORY-INTERFACES]

Q: Why is effective DDR bandwidth below peak?

A:
Refresh, bank conflicts, read/write turnaround, and command scheduling overhead.

FOLLOW-UP TRAP: Multiplying width×freq only.

What does training establish?

[INT][PROT][MEMORY-INTERFACES]

Q: What does training establish?

A:
DQS/DQ timing alignment and voltage margins so reads/writes work across PVT.

FOLLOW-UP TRAP: Assuming training is one-time for life of product.

Row hit vs row miss — which is faster?

[INT][PROT][MEMORY-INTERFACES]

Q: Row hit vs row miss — which is faster?

A:
Row hit (page open); miss requires precharge+activate penalty.

FOLLOW-UP TRAP: Ignoring address interleave and stride.

Q&A drill guide

LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSION

Sketch while answering

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Common traps

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.