Training & Timing Modes

What this topic teaches

Training & Timing Modes is about converting a protocol rule into a measurable silicon contract. training aligns DQS/DQ timing and voltage margins so digital transfers survive PVT and board/package variation. The hard part is never the happy-path diagram; it is proving, under real traffic, which layer and which transaction broke the contract.

The senior-engineer question

When training margin, eye width, boot failure rate moves, can you identify the transaction, the protocol layer, the responsible owner, and the smallest experiment that proves the root cause?

PROTOCOL STACK VIEW — Training & Timing Modes

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

Picture the protocol

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

Read eye diagram

READ DATA EYE (sample in the center of the opening)

voltage
  ^      ____________
  |     /            \        <- wider eye = more margin
  |    /   sample     \
  |   |      .         |
  |    \              /
  |     \____________/
  +-------------------------> time (DQS phase)
        ^           ^
     left edge   right edge
   center = (left+right)/2  -> training picks this point

Training sequence

BRING-UP TRAINING ORDER

1. CA training      (command/address alignment)
2. Write leveling   (align DQS to CLK at DRAM)
3. Read training    (gate + per-bit deskew + Vref)
4. Write training   (per-bit deskew + Vref)
5. Lock + store margins

A failed boot usually stops at one of these steps -> read the transcript.

Transaction sequence

SEQUENCE — Training & Timing Modes

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: training margin, eye width, boot failure rate

Who owns which layer

LAYER RESPONSIBILITY — Training & Timing Modes

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Evidence to collect

• Primary metric: training margin, eye width, boot failure rate.

• Primary artifact: training transcript, margin report, mode register dump.

• Owners to bring into review: bring-up owner, PHY owner, board owner.

• Spec clause or requirement ID for every claim.

• One traffic replay that fails and one reduced sequence that isolates the rule.

Ownership map

OWNERSHIP MAP — Training & Timing Modes

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        bring-up owner
spec/VIP            PHY owner
firmware/system     board owner

Rule: every metric must have a named owner before a review starts.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Carry transaction identity across waveform, log, counter, and spec view.

• Separate protocol violation, integration configuration, and performance bottleneck before proposing a fix.

• Draw the diagram first; the waveform should confirm the picture, not replace it.

Common pitfalls

• Debugging only one channel or layer.

• Treating a VIP error message as root cause instead of evidence.

• Quoting peak interface bandwidth without payload efficiency.

Protocol deep dive

DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

Concept diagram

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Metric graph

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.

Metrics and artifacts to collect

• effective BW

• row hit rate

• refresh stall %

• training margin

• ECC error log

Mini case study

Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

Debug branches

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.