Worked example

Worked Example for Memory Interface Debug focuses on ECC error rate, read timeout count, bandwidth regression. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

A product workload shows ECC error rate, read timeout count, bandwidth regression. The first review mistake is to blame the whole interface. A better review starts by pinning one transaction, proving where protocol progress stopped, and checking whether the observed behavior is legal for Memory Interface Debug.

Sequence under inspection

SEQUENCE — Memory Interface Debug

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: ECC error rate, read timeout count, bandwidth regression

Memory debug funnel

MEMORY DEBUG FUNNEL

symptom: ECC errors / timeouts / bandwidth drop
   |
   v  is it ALL addresses or a region?
region --> address map / interleave bug
   |
   v  is it after a thermal/voltage change?
yes --> training margin / PVT
   |
   v  only under mixed traffic?
yes --> scheduler / QoS / refresh contention

1. Capture the failing waveform and transaction log.

2. Tag the request ID, address, endpoint, or lane.

3. Find the first response, retry, stall, or missing completion.

4. Compare against ECC log, address decoder trace, training delta, traffic replay.

5. Choose one reversible fix and write the regression list before editing RTL or firmware.

Did the fix work?

BEFORE / AFTER — Memory Interface Debug

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

Concept diagram

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Metric graph

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.

Metrics and artifacts to collect

• effective BW

• row hit rate

• refresh stall %

• training margin

• ECC error log

Mini case study

Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

Debug branches

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Narrative walkthrough

A team sees ECC error rate, read timeout count, bandwidth regression drop 40% after a seemingly small change near Memory Interface Debug.

They almost widen the interface. Instead they capture id=7 read burst and find W beats never matched AW len.