Design space exploration

For DDR Controller / PHY Split, senior architects map options against command efficiency, PHY training pass rate, read/write turnaround loss on the product workload — not on a single directed test.

Option A — conservative

• Minimal / simple: helps timing, area, verification

• Risk: bandwidth and latency tails

• Validate with: control paths and low-rate peripherals

Option B — buffered / outstanding

• Buffered / outstanding: helps throughput under latency

• Risk: deadlock and debug complexity

• Validate with: DMA and memory-class traffic

Option C — QoS / arbitration

• QoS / arbitration: helps product-critical traffic wins

• Risk: verification state explosion

• Validate with: mixed CPU/GPU/DMA SoCs

Option D — software-first

• Software contract: helps predictable programming model

• Risk: portability and driver cost

• Validate with: platforms with long SW lifetime

DESIGN SPACE — DDR Controller / PHY Split

        performance
            ^
            |     [C] QoS-heavy
            |        *
            |   [B] buffered *
            |              *
            | [A] simple *
            +--------------------> complexity
                      [D] SW-first

Pick the smallest option that moves command efficiency, PHY training pass rate, read/write turnaround loss on the product workload.

Design pitfalls

• Sizing for peak headline bandwidth instead of payload efficiency

• Adding outstanding depth without ordering analysis

• Choosing aggressive hardware before a reduced sequence proves the mechanism

Tradeoff curve

BEFORE / AFTER — DDR Controller / PHY Split

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

Concept diagram

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Metric graph

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.

Metrics and artifacts to collect

• effective BW

• row hit rate

• refresh stall %

• training margin

• ECC error log

Mini case study

Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

Debug branches

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read DDR Controller / PHY Split against one concrete product workload, not a synthetic directed test.

the controller schedules memory commands while the PHY handles electrical timing, calibration, and lane alignment.