DDR Controller / PHY Split: Software / Programmer View

Software and programmer view

Firmware training, mode registers, and interleave policy are part of the protocol contract.

What programmers feel

• Timeouts with healthy-looking hardware counters

• Data corruption without obvious ECC/CRC

• Ordering surprises under multi-threaded drivers

• Performance cliffs when payload size changes

API / driver implications

• Descriptor alignment and cache line sharing

• Fence/barrier placement around DMA

• IRQ type (level vs edge) and clear sequence

• Memory-mapped register access ordering

Compiler and runtime interaction

• Volatile and barrier semantics for device memory

• Struct padding affecting burst efficiency

• Batching policy in userspace drivers

Software-side mitigations

• Pad structures to cache lines

• Pin buffers and use coherent DMA where required

• Expose hardware counters to software profilers

• Document legal outstanding depth and ordering

SOFTWARE EXAMPLE — DDR Controller / PHY Split

// Bad: assumes ordering across unrelated IDs without fence
dma_start(ch0); dma_start(ch1); cpu_read(result); // may see stale

// Better: document which completions are ordered and insert barrier
dma_start(ch0); wait_completion(ch0); cpu_read(result);

Layer the driver touches

LAYER RESPONSIBILITY — DDR Controller / PHY Split

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

Concept diagram

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Metric graph

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.

Metrics and artifacts to collect

• effective BW

• row hit rate

• refresh stall %

• training margin

• ECC error log

Mini case study

Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

Debug branches

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read DDR Controller / PHY Split against one concrete product workload, not a synthetic directed test.

the controller schedules memory commands while the PHY handles electrical timing, calibration, and lane alignment.