PROMPT
You see command efficiency, PHY training pass rate, read/write turnaround loss on DDR Controller / PHY Split. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains the controller schedules memory commands while the PHY handles electrical timing, calibration, and lane alignment.
3. Requests controller command trace, PHY training log, timing mode table.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

MEMORY STACK

  [ requestors ] --AXI/CHI--> [ MEMORY CONTROLLER ]
                                |  schedule, reorder, refresh
                                v
                              [ PHY ]
                                |  DQS/DQ timing, training, calibration
                                v
                              [ DRAM ]  banks / rows / columns

Controller thinks in transactions; PHY thinks in picoseconds.

ROOT-CAUSE TREE — DDR Controller / PHY Split

command efficiency, PHY training pass rate, read/write turnaround loss looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

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