DDR Controller / PHY Split: Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Follow this when you own DDR Controller / PHY Split in a protocol review or bring-up war room.

1. State expected transaction in plain language (who initiates, what completes).

2. Draw layer stack and mark clock/reset boundaries.

3. List channels: request, data, response, snoop, credit, or lane.

4. Tag ID/address/endpoint on the failing run.

5. Find first cycle where progress stops or semantics change.

6. Check bridge: width, ID remap, burst, ordering attributes.

7. Check flow control: ready, credit, FIFO, link state.

8. Check firmware/register mode vs hardware capability.

9. Build minimal replay; confirm legal vs illegal per spec.

10. Estimate metric delta from proposed fix.

11. Run compliance + product traffic regression matrix.

12. Write signoff memo with owners and artifacts attached.

Artifacts to collect

• controller command trace, PHY training log, timing mode table

• VIP transaction log

• Waveform with annotations

• Spec clause reference

• Regression manifest

Decision memo template

PROTOCOL DECISION MEMO — DDR Controller / PHY Split
metric:
transaction id:
layer:
hypothesis:
experiment:
fix:
validation:
owners: memory controller owner, PHY owner, SoC integration owner

Reference visuals

Controller / PHY responsibility split

MEMORY STACK

  [ requestors ] --AXI/CHI--> [ MEMORY CONTROLLER ]
                                |  schedule, reorder, refresh
                                v
                              [ PHY ]
                                |  DQS/DQ timing, training, calibration
                                v
                              [ DRAM ]  banks / rows / columns

Controller thinks in transactions; PHY thinks in picoseconds.

Protocol deep dive

DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

Concept diagram

MEMORY PATH

masters -> controller scheduler -> PHY -> DRAM banks
              |                      |
         refresh/QoS            training/margin

Scheduler sees transactions; PHY sees picoseconds.

Metric graph

BANDWIDTH LOSS WATERFALL

peak              ████████████████████████
refresh           █████████████████████
turnaround        ██████████████████
row miss          ██████████████
effective         ██████████████

Quote the bottom bar in reviews.

Metrics and artifacts to collect

• effective BW

• row hit rate

• refresh stall %

• training margin

• ECC error log

Mini case study

Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

Debug branches

• If ECC errors, check training margin and address interleave first.

• If BW low with high row hit, suspect port arbitration not DRAM.

• If boot fail, stop at training step in transcript.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read DDR Controller / PHY Split against one concrete product workload, not a synthetic directed test.

the controller schedules memory commands while the PHY handles electrical timing, calibration, and lane alignment.