Integration review: command efficiency, PHY training pass rate, read/write turnaround loss regresses after a change touching DDR Controller / PHY Split.
Baseline traffic passed compliance and performance targets. A bridge update, firmware change, or clock/reset tweak introduced intermittent failures visible only under mixed traffic.
Regression in command efficiency, PHY training pass rate, read/write turnaround loss
VIP warning followed by software timeout (symptom lag)
Directed tests pass; stress or product replay fails
Two teams disagree because they look at different layers
Hour 0: freeze sim tag, firmware, and spec revision
Hour 1: capture first failing transaction with ID/address
Hour 2: correlate waveform, VIP monitor, and counter
Hour 3: classify: rule violation vs config vs timing vs load
Hour 4: reduce to 3-transaction minimal sequence
Hour 5: bounded RTL or register fix + regression list
Hour 6: compliance replay + product workload signoff memo
Controller issued reads during refresh window that PHY had not advertised as ready, causing intermittent read timeouts.
Minimal reversible change at the owning boundary
Re-run controller command trace, PHY training log, timing mode table on failing and baseline seeds
Compliance suite + mixed-traffic regression
Document software-visible impact and waiver if any
First bad transaction beats loudest timeout
Layer alignment across RTL, VIP, firmware, and analyzer
Performance and correctness regressions need separate evidence
CASE STUDY METRICS — DDR Controller / PHY Split
baseline command efficiency, PHY training pass rate, read/write turnaround loss: within target
regressed command efficiency, PHY training pass rate, read/write turnaround loss: fails product threshold
after fix command efficiency, PHY training pass rate, read/write turnaround loss: restored + compliance PASS
residual risk: document waiver or monitor in fieldSEQUENCE — DDR Controller / PHY Split
initiator interconnect/PHY target
| request (id) -------> | |
| | forward ----------> |
| | | work
| | <---- response ---- |
| <----- complete ------ | |
|
metric captured here: command efficiency, PHY training pass rate, read/write turnaround lossDDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.
MEMORY PATH
masters -> controller scheduler -> PHY -> DRAM banks
| |
refresh/QoS training/margin
Scheduler sees transactions; PHY sees picoseconds.BANDWIDTH LOSS WATERFALL
peak ████████████████████████
refresh █████████████████████
turnaround ██████████████████
row miss ██████████████
effective ██████████████
Quote the bottom bar in reviews.effective BW
row hit rate
refresh stall %
training margin
ECC error log
Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.
If ECC errors, check training margin and address interleave first.
If BW low with high row hit, suspect port arbitration not DRAM.
If boot fail, stop at training step in transcript.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Mixed traffic exposed a bug that single-master directed tests missed for three weeks.
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