Use these drills after completing all topics in Coherence Fabrics (ACE / CHI). Answer with layer, transaction, metric, artifact, and regression.
[INT][PROT][COHERENCE-FABRICS]
Q: What is false sharing?
A:
Different variables on the same cache line cause coherence traffic without logical data sharing.
FOLLOW-UP TRAP: Fixing with a faster NoC only.[INT][PROT][COHERENCE-FABRICS]
Q: What does the Shared state mean in MESI?
A:
Line is valid and may be shared; reads allowed, writes require upgrade/invalidate sequence.
FOLLOW-UP TRAP: Confusing Shared with Exclusive.[INT][PROT][COHERENCE-FABRICS]
Q: Why does CHI separate request, response, data, and snoop flows?
A:
To scale many-core systems with independent channels and avoid protocol deadlock.
FOLLOW-UP TRAP: Treating CHI as 'AXI with snoops'.LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSIONCOHERENCE TRAFFIC FLOW
RN issues coherent read
-> HN looks up directory
-> snoops to sharers
-> data + state update returned
False sharing: different variables, same cache line -> coherence storm.If snoop latency high, check home node placement and directory policy.
If ordering bug, run litmus sequences before microarch changes.
If traffic storm, profile cache line sharing in software layout.
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.