Interface Protocols · All levels

ACE Coherent Transactions

Coherence Fabrics (ACE / CHI): ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing.

What this topic teaches

ACE Coherent Transactions is about converting a protocol rule into a measurable silicon contract. ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing. The hard part is never the happy-path diagram; it is proving, under real traffic, which layer and which transaction broke the contract.

The senior-engineer question

When snoop latency, intervention rate, clean/dirty transfer mix moves, can you identify the transaction, the protocol layer, the responsible owner, and the smallest experiment that proves the root cause?

diagram

PROTOCOL STACK VIEW — ACE Coherent Transactions

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

Picture the protocol

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

MESI state diagram

diagram

MESI CACHE LINE STATES

        read miss
   I ----------------> S  (shared, clean)
   |  \                 |
   |   \ write miss     | local write
   |    \               v
   |     +----------->  M  (modified, dirty, exclusive)
   |                    ^
   | read (no sharer)   |
   +-----------------> E (exclusive, clean) --write--> M

snoop read hits M -> downgrade to S and write back
snoop write hits M/E/S -> invalidate to I

Snoop intervention sequence

diagram

SNOOP INTERVENTION (cache-to-cache transfer)

CPU0 (has line M)      Fabric/Home        CPU1 (wants line)
      |                    |                    |
      |                    | <----- ReadShared--|
      | <----- Snoop ------|                    |
      |-- data + downgrade>|                    |
      |                    |----- data -------->|
      |   (M -> S)         |              (I -> S)

Metric to watch: intervention latency and snoop response time.

Transaction sequence

diagram

SEQUENCE — ACE Coherent Transactions

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: snoop latency, intervention rate, clean/dirty transfer mix

Who owns which layer

diagram

LAYER RESPONSIBILITY — ACE Coherent Transactions

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Evidence to collect

Primary metric: snoop latency, intervention rate, clean/dirty transfer mix.
Primary artifact: ACE channel trace, coherency state table, snoop response log.
Owners to bring into review: coherency architect, CPU subsystem owner, VIP owner.
Spec clause or requirement ID for every claim.
One traffic replay that fails and one reduced sequence that isolates the rule.

Ownership map

diagram

OWNERSHIP MAP — ACE Coherent Transactions

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        coherency architect
spec/VIP            CPU subsystem owner
firmware/system     VIP owner

Rule: every metric must have a named owner before a review starts.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

Carry transaction identity across waveform, log, counter, and spec view.
Separate protocol violation, integration configuration, and performance bottleneck before proposing a fix.
Draw the diagram first; the waveform should confirm the picture, not replace it.

Common pitfalls

Debugging only one channel or layer.
Treating a VIP error message as root cause instead of evidence.
Quoting peak interface bandwidth without payload efficiency.

Protocol deep dive

Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.

Concept diagram

diagram

COHERENCE TRAFFIC FLOW

RN issues coherent read
   -> HN looks up directory
   -> snoops to sharers
   -> data + state update returned

False sharing: different variables, same cache line -> coherence storm.

Metric graph

diagram

COHERENCY TRAFFIC STACK

data fetch        ████████
snoop responses   ██████████████
writebacks        ██████
maintenance ops   ████

High snoop stack with good IPC -> suspect line sharing before faster NoC.

Metrics and artifacts to collect

snoop rate
intervention latency
coherency transaction mix
false sharing indicators

Mini case study

Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.

Debug branches

If snoop latency high, check home node placement and directory policy.
If ordering bug, run litmus sequences before microarch changes.
If traffic storm, profile cache line sharing in software layout.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Practice this lesson