Interface Protocols · All levels

ACE Coherent Transactions: Mechanism

Mechanism for ACE Coherent Transactions.

Mechanism to understand

Mechanism for ACE Coherent Transactions focuses on snoop latency, intervention rate, clean/dirty transfer mix. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing. Think of it as a contract enforced at boundaries: the sender promises stability and legality, the receiver promises forward progress, and the fabric in between promises not to silently change identity or ordering.

Identify the transaction boundary: request, data, response, completion, or retry.
Identify the flow-control boundary: valid/ready, grant, credit, FIFO depth, or lane state.
Identify what the receiver is allowed to assume and what the sender must hold stable.

Layered view

diagram

PROTOCOL STACK VIEW — ACE Coherent Transactions

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

MESI state diagram

diagram

MESI CACHE LINE STATES

        read miss
   I ----------------> S  (shared, clean)
   |  \                 |
   |   \ write miss     | local write
   |    \               v
   |     +----------->  M  (modified, dirty, exclusive)
   |                    ^
   | read (no sharer)   |
   +-----------------> E (exclusive, clean) --write--> M

snoop read hits M -> downgrade to S and write back
snoop write hits M/E/S -> invalidate to I

Snoop intervention sequence

diagram

SNOOP INTERVENTION (cache-to-cache transfer)

CPU0 (has line M)      Fabric/Home        CPU1 (wants line)
      |                    |                    |
      |                    | <----- ReadShared--|
      | <----- Snoop ------|                    |
      |-- data + downgrade>|                    |
      |                    |----- data -------->|
      |   (M -> S)         |              (I -> S)

Metric to watch: intervention latency and snoop response time.

Layer responsibilities

diagram

LAYER RESPONSIBILITY — ACE Coherent Transactions

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.

Concept diagram

diagram

COHERENCE TRAFFIC FLOW

RN issues coherent read
   -> HN looks up directory
   -> snoops to sharers
   -> data + state update returned

False sharing: different variables, same cache line -> coherence storm.

Metric graph

diagram

COHERENCY TRAFFIC STACK

data fetch        ████████
snoop responses   ██████████████
writebacks        ██████
maintenance ops   ████

High snoop stack with good IPC -> suspect line sharing before faster NoC.

Metrics and artifacts to collect

snoop rate
intervention latency
coherency transaction mix
false sharing indicators

Mini case study

Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.

Debug branches

If snoop latency high, check home node placement and directory policy.
If ordering bug, run litmus sequences before microarch changes.
If traffic storm, profile cache line sharing in software layout.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Mechanism deep dive

ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing.

Walk the transaction forward: request accepted → data moves → response completes → software visible effect.

Practice this lesson