ACE Coherent Transactions: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for ACE Coherent Transactions focuses on snoop latency, intervention rate, clean/dirty transfer mix. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

Treat these as a signed interface contract. Ambiguity here is the single biggest source of wasted integration weeks, because two teams debug against different assumptions.

INPUTS
  - protocol spec revision and feature subset
  - clock/reset assumptions
  - address map, ID/tag width, ordering attributes
  - traffic class, QoS, firmware register settings

OUTPUTS
  - legal transaction trace
  - integration waiver list
  - VIP/compliance report
  - owner-signed debug or signoff note

Transaction sequence

SEQUENCE — ACE Coherent Transactions

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: snoop latency, intervention rate, clean/dirty transfer mix

Ownership map

OWNERSHIP MAP — ACE Coherent Transactions

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        coherency architect
spec/VIP            CPU subsystem owner
firmware/system     VIP owner

Rule: every metric must have a named owner before a review starts.

Protocol deep dive

Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.

Concept diagram

COHERENCE TRAFFIC FLOW

RN issues coherent read
   -> HN looks up directory
   -> snoops to sharers
   -> data + state update returned

False sharing: different variables, same cache line -> coherence storm.

Metric graph

COHERENCY TRAFFIC STACK

data fetch        ████████
snoop responses   ██████████████
writebacks        ██████
maintenance ops   ████

High snoop stack with good IPC -> suspect line sharing before faster NoC.

Metrics and artifacts to collect

• snoop rate

• intervention latency

• coherency transaction mix

• false sharing indicators

Mini case study

Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.

Debug branches

• If snoop latency high, check home node placement and directory policy.

• If ordering bug, run litmus sequences before microarch changes.

• If traffic storm, profile cache line sharing in software layout.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read ACE Coherent Transactions against one concrete product workload, not a synthetic directed test.

ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing.