ACE Coherent Transactions: Interview Drills

PROMPT
You see snoop latency, intervention rate, clean/dirty transfer mix on ACE Coherent Transactions. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing.
3. Requests ACE channel trace, coherency state table, snoop response log.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

MESI CACHE LINE STATES

        read miss
   I ----------------> S  (shared, clean)
   |  \                 |
   |   \ write miss     | local write
   |    \               v
   |     +----------->  M  (modified, dirty, exclusive)
   |                    ^
   | read (no sharer)   |
   +-----------------> E (exclusive, clean) --write--> M

snoop read hits M -> downgrade to S and write back
snoop write hits M/E/S -> invalidate to I

ROOT-CAUSE TREE — ACE Coherent Transactions

snoop latency, intervention rate, clean/dirty transfer mix looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

COHERENCE TRAFFIC FLOW

RN issues coherent read
   -> HN looks up directory
   -> snoops to sharers
   -> data + state update returned

False sharing: different variables, same cache line -> coherence storm.

COHERENCY TRAFFIC STACK

data fetch        ████████
snoop responses   ██████████████
writebacks        ██████
maintenance ops   ████

High snoop stack with good IPC -> suspect line sharing before faster NoC.