MESI/MOESI/CHI differ in traffic, directory cost, latency, and verification burden.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Non-shareable | fast | no coherency | device mem |
| Shareable | coherent | snoop traffic | SMP |
| ACE snoop | correctness | latency | CPU cluster |
| CHI home | scalable | complex | many-core |
+------------------+----------------+----------------+----------------+Pick baseline when schedule and risk dominate
Pick buffering only after proving backpressure is the limiter
Pick width only after payload efficiency analysis
Pick software contract when hardware change is too expensive
Comparing peak spec numbers across protocols
Ignoring bridge and firmware in the comparison
One-size-fits-all answer in interviews
COMPLIANCE / DEBUG MATRIX — ACE Coherent Transactions
+-------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------+------------------------+--------------------------+-------------------------+
| Waveform | signal-level sequence | full system intent | map to transaction log |
| VIP transaction | spec-level behavior | RTL micro-cause | correlate timestamp |
| Counter / PMU | aggregate symptom | single failing packet | isolate traffic class |
| Firmware log | software-visible flow | electrical/link health | compare with hardware |
| Analyzer capture | external protocol view | internal reset/config | align with RTL trace |
+-------------------+------------------------+--------------------------+-------------------------+Coherence extends memory transactions with snoop and state — traffic multiplies when software shares cache lines.
COHERENCE TRAFFIC FLOW
RN issues coherent read
-> HN looks up directory
-> snoops to sharers
-> data + state update returned
False sharing: different variables, same cache line -> coherence storm.COHERENCY TRAFFIC STACK
data fetch ████████
snoop responses ██████████████
writebacks ██████
maintenance ops ████
High snoop stack with good IPC -> suspect line sharing before faster NoC.snoop rate
intervention latency
coherency transaction mix
false sharing indicators
Benchmark IPC looked fine but system power spiked: per-core counters were on one cache line. Padding counters fixed coherency traffic without any NoC change.
If snoop latency high, check home node placement and directory policy.
If ordering bug, run litmus sequences before microarch changes.
If traffic storm, profile cache line sharing in software layout.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Re-read ACE Coherent Transactions against one concrete product workload, not a synthetic directed test.
ACE extends AXI with snoop and barrier behavior so masters can participate in coherent sharing.
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