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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
    • DDR Controller / PHY Split
    • Training & Timing Modes
    • Refresh & Bandwidth Efficiency
      • Refresh & Bandwidth Efficiency: Mechanism
      • Refresh & Bandwidth Efficiency: Inputs & Outputs
      • Refresh & Bandwidth Efficiency: Reports & Metrics
      • Refresh & Bandwidth Efficiency: Debug Playbook
      • Refresh & Bandwidth Efficiency: Worked Example
      • Refresh & Bandwidth Efficiency: Pitfalls & Red Flags
      • Refresh & Bandwidth Efficiency: Interview Drills
      • Refresh & Bandwidth Efficiency: Review Checklist
      • Refresh & Bandwidth Efficiency: Theory Deep Dive
      • Refresh & Bandwidth Efficiency: Design Space
      • Refresh & Bandwidth Efficiency: Expanded Case Study
      • Refresh & Bandwidth Efficiency: Step-by-Step Walkthrough
      • Refresh & Bandwidth Efficiency: Comparison Matrix
      • Refresh & Bandwidth Efficiency: Software / Programmer View
      • Refresh & Bandwidth Efficiency: Silicon PPA Impact
    • Memory Interface Debug
    • Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Refresh & Bandwidth Efficiency
  1. Topics
  2. Bus Protocols
  3. Memory Interfaces (DDR / LPDDR / HBM)
  4. Refresh & Bandwidth Efficiency
  5. Refresh & Bandwidth Efficiency: Expanded Case Study

Interface Protocols · All levels

Refresh & Bandwidth Efficiency: Expanded Case Study

Expanded Case Study for Refresh & Bandwidth Efficiency.

On this page

    Extended case study

    Integration review: effective bandwidth, row-hit rate, refresh stall percentage regresses after a change touching Refresh & Bandwidth Efficiency.

    Background

    Baseline traffic passed compliance and performance targets. A bridge update, firmware change, or clock/reset tweak introduced intermittent failures visible only under mixed traffic.

    Symptoms observed

    • Regression in effective bandwidth, row-hit rate, refresh stall percentage

    • VIP warning followed by software timeout (symptom lag)

    • Directed tests pass; stress or product replay fails

    • Two teams disagree because they look at different layers

    Investigation timeline

    1. Hour 0: freeze sim tag, firmware, and spec revision

    2. Hour 1: capture first failing transaction with ID/address

    3. Hour 2: correlate waveform, VIP monitor, and counter

    4. Hour 3: classify: rule violation vs config vs timing vs load

    5. Hour 4: reduce to 3-transaction minimal sequence

    6. Hour 5: bounded RTL or register fix + regression list

    7. Hour 6: compliance replay + product workload signoff memo

    Root cause

    The failing behavior traced to a violated assumption in Refresh & Bandwidth Efficiency: refresh, bank conflicts, turnaround, and command scheduling reduce useful bandwidth below headline bus width.

    Fix and validation

    • Minimal reversible change at the owning boundary

    • Re-run bandwidth efficiency stack, bank conflict histogram, traffic class report on failing and baseline seeds

    • Compliance suite + mixed-traffic regression

    • Document software-visible impact and waiver if any

    Lessons learned

    • First bad transaction beats loudest timeout

    • Layer alignment across RTL, VIP, firmware, and analyzer

    • Performance and correctness regressions need separate evidence

    Diagram
    CASE STUDY METRICS — Refresh & Bandwidth Efficiency
    
    baseline     effective bandwidth, row-hit rate, refresh stall percentage: within target
    regressed    effective bandwidth, row-hit rate, refresh stall percentage: fails product threshold
    after fix    effective bandwidth, row-hit rate, refresh stall percentage: restored + compliance PASS
    residual risk: document waiver or monitor in field

    Sequence under stress

    Diagram
    SEQUENCE — Refresh & Bandwidth Efficiency
    
      initiator            interconnect/PHY            target
          |  request (id) ------->  |                     |
          |                         |  forward ----------> |
          |                         |                     | work
          |                         |  <---- response ---- |
          |  <----- complete ------ |                     |
          |
       metric captured here: effective bandwidth, row-hit rate, refresh stall percentage

    Protocol deep dive

    DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.

    Concept diagram

    Diagram
    MEMORY PATH
    
    masters -> controller scheduler -> PHY -> DRAM banks
                  |                      |
             refresh/QoS            training/margin
    
    Scheduler sees transactions; PHY sees picoseconds.

    Metric graph

    Diagram
    BANDWIDTH LOSS WATERFALL
    
    peak              ████████████████████████
    refresh           █████████████████████
    turnaround        ██████████████████
    row miss          ██████████████
    effective         ██████████████
    
    Quote the bottom bar in reviews.

    Metrics and artifacts to collect

    • effective BW

    • row hit rate

    • refresh stall %

    • training margin

    • ECC error log

    Mini case study

    Video workload lost half effective bandwidth after firmware enabled aggressive low-power refresh. Scheduler and firmware QoS had to be co-designed.

    Debug branches

    • If ECC errors, check training margin and address interleave first.

    • If BW low with high row hit, suspect port arbitration not DRAM.

    • If boot fail, stop at training step in transcript.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Field case notes

    Mixed traffic exposed a bug that single-master directed tests missed for three weeks.

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    PreviousNext: Refresh & Bandwidth Efficiency: Step-by-Step Walkthrough

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    See also

    • Refresh & Bandwidth Efficiency: Mechanism
    • Refresh & Bandwidth Efficiency: Inputs & Outputs
    • Refresh & Bandwidth Efficiency: Reports & Metrics