Embedded Peripherals (I2C / SPI / UART): Tricky Q&A

Section Q&A bank

Use these drills after completing all topics in Embedded Peripherals (I2C / SPI / UART). Answer with layer, transaction, metric, artifact, and regression.

I2C NACK — what are common causes?

[INT][PROT][EMBEDDED-PERIPHERALS]

Q: I2C NACK — what are common causes?

A:
Wrong address, device not ready, clock stretch timeout, missing pull-ups, speed too high.

FOLLOW-UP TRAP: Only checking software address once.

SPI mode mismatch symptom?

[INT][PROT][EMBEDDED-PERIPHERALS]

Q: SPI mode mismatch symptom?

A:
Shifted/wrong bits; looks like random data.

FOLLOW-UP TRAP: Changing clock speed without CPOL/CPHA.

UART overrun cause?

[INT][PROT][EMBEDDED-PERIPHERALS]

Q: UART overrun cause?

A:
ISR too slow, FIFO too shallow, or baud mismatch.

FOLLOW-UP TRAP: Blaming the external device.

Q&A drill guide

LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSION

Sketch while answering

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Common traps

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.