UART Flow Control

What this topic teaches

UART Flow Control is about converting a protocol rule into a measurable silicon contract. UART converts bytes to asynchronous serial frames and depends on baud tolerance, FIFO depth, and flow control. The hard part is never the happy-path diagram; it is proving, under real traffic, which layer and which transaction broke the contract.

The senior-engineer question

When overrun count, baud mismatch, interrupt service latency moves, can you identify the transaction, the protocol layer, the responsible owner, and the smallest experiment that proves the root cause?

PROTOCOL STACK VIEW — UART Flow Control

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

Picture the protocol

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

UART frame

UART FRAME (8N1)

idle ‾‾‾‾\__ D0 D1 D2 D3 D4 D5 D6 D7 /‾‾‾ idle
         ^start          (LSB first)   ^stop
no shared clock: both sides must agree on baud within ~2-3%

RTS/CTS flow control

RTS/CTS HANDSHAKE

receiver RTS (i can take data) ‾‾‾‾\____/‾‾‾
sender checks CTS before sending more
FIFO near full -> drop RTS -> sender pauses -> no overrun

Transaction sequence

SEQUENCE — UART Flow Control

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: overrun count, baud mismatch, interrupt service latency

Who owns which layer

LAYER RESPONSIBILITY — UART Flow Control

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Evidence to collect

• Primary metric: overrun count, baud mismatch, interrupt service latency.

• Primary artifact: RX/TX waveform, FIFO watermark log, driver ISR trace.

• Owners to bring into review: firmware owner, peripheral RTL owner, validation owner.

• Spec clause or requirement ID for every claim.

• One traffic replay that fails and one reduced sequence that isolates the rule.

Ownership map

OWNERSHIP MAP — UART Flow Control

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        firmware owner
spec/VIP            peripheral RTL owner
firmware/system     validation owner

Rule: every metric must have a named owner before a review starts.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Carry transaction identity across waveform, log, counter, and spec view.

• Separate protocol violation, integration configuration, and performance bottleneck before proposing a fix.

• Draw the diagram first; the waveform should confirm the picture, not replace it.

Common pitfalls

• Debugging only one channel or layer.

• Treating a VIP error message as root cause instead of evidence.

• Quoting peak interface bandwidth without payload efficiency.

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

• NACK rate

• overrun count

• CS setup/hold violations

• IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.