UART Flow Control: Design Space

Design space exploration

For UART Flow Control, senior architects map options against overrun count, baud mismatch, interrupt service latency on the product workload — not on a single directed test.

Option A — conservative

• Minimal / simple: helps timing, area, verification

• Risk: bandwidth and latency tails

• Validate with: control paths and low-rate peripherals

Option B — buffered / outstanding

• Buffered / outstanding: helps throughput under latency

• Risk: deadlock and debug complexity

• Validate with: DMA and memory-class traffic

Option C — QoS / arbitration

• QoS / arbitration: helps product-critical traffic wins

• Risk: verification state explosion

• Validate with: mixed CPU/GPU/DMA SoCs

Option D — software-first

• Software contract: helps predictable programming model

• Risk: portability and driver cost

• Validate with: platforms with long SW lifetime

DESIGN SPACE — UART Flow Control

        performance
            ^
            |     [C] QoS-heavy
            |        *
            |   [B] buffered *
            |              *
            | [A] simple *
            +--------------------> complexity
                      [D] SW-first

Pick the smallest option that moves overrun count, baud mismatch, interrupt service latency on the product workload.

Design pitfalls

• Sizing for peak headline bandwidth instead of payload efficiency

• Adding outstanding depth without ordering analysis

• Choosing aggressive hardware before a reduced sequence proves the mechanism

Tradeoff curve

BEFORE / AFTER — UART Flow Control

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

• NACK rate

• overrun count

• CS setup/hold violations

• IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read UART Flow Control against one concrete product workload, not a synthetic directed test.

UART converts bytes to asynchronous serial frames and depends on baud tolerance, FIFO depth, and flow control.