UART Flow Control: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for UART Flow Control focuses on overrun count, baud mismatch, interrupt service latency. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

Treat these as a signed interface contract. Ambiguity here is the single biggest source of wasted integration weeks, because two teams debug against different assumptions.

INPUTS
  - protocol spec revision and feature subset
  - clock/reset assumptions
  - address map, ID/tag width, ordering attributes
  - traffic class, QoS, firmware register settings

OUTPUTS
  - legal transaction trace
  - integration waiver list
  - VIP/compliance report
  - owner-signed debug or signoff note

Transaction sequence

SEQUENCE — UART Flow Control

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: overrun count, baud mismatch, interrupt service latency

Ownership map

OWNERSHIP MAP — UART Flow Control

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        firmware owner
spec/VIP            peripheral RTL owner
firmware/system     validation owner

Rule: every metric must have a named owner before a review starts.

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

• NACK rate

• overrun count

• CS setup/hold violations

• IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read UART Flow Control against one concrete product workload, not a synthetic directed test.

UART converts bytes to asynchronous serial frames and depends on baud tolerance, FIFO depth, and flow control.