Interface Protocols · All levels

UART Flow Control: Comparison Matrix

Comparison Matrix for UART Flow Control.

Comparison matrix

FIFO depth, interrupt policy, and DMA burst size determine real peripheral throughput.

diagram

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Baseline         | known, signed  | may miss peak  | shipping SKU   |
| More buffer      | absorbs latency | area, deadlock | DMA-heavy      |
| Wider bus        | peak BW up     | timing, power  | memory bound   |
| SW contract      | cheap silicon  | driver burden  | fixed platform |
+------------------+----------------+----------------+----------------+

When to choose each approach

Pick baseline when schedule and risk dominate
Pick buffering only after proving backpressure is the limiter
Pick width only after payload efficiency analysis
Pick software contract when hardware change is too expensive

Interview traps

Comparing peak spec numbers across protocols
Ignoring bridge and firmware in the comparison
One-size-fits-all answer in interviews

Evidence comparison

diagram

COMPLIANCE / DEBUG MATRIX — UART Flow Control

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| Waveform           | signal-level sequence  | full system intent       | map to transaction log  |
| VIP transaction    | spec-level behavior    | RTL micro-cause          | correlate timestamp     |
| Counter / PMU      | aggregate symptom      | single failing packet    | isolate traffic class   |
| Firmware log       | software-visible flow  | electrical/link health   | compare with hardware   |
| Analyzer capture   | external protocol view | internal reset/config    | align with RTL trace    |
+-------------------+------------------------+--------------------------+-------------------------+

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

diagram

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

NACK rate
overrun count
CS setup/hold violations
IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

If overrun, FIFO depth vs ISR latency vs DMA burst.
If NACK on I2C, pull-ups, speed, and clock stretch.
If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read UART Flow Control against one concrete product workload, not a synthetic directed test.

UART converts bytes to asynchronous serial frames and depends on baud tolerance, FIFO depth, and flow control.

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