UART Flow Control: Interview Drills

PROMPT
You see overrun count, baud mismatch, interrupt service latency on UART Flow Control. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains UART converts bytes to asynchronous serial frames and depends on baud tolerance, FIFO depth, and flow control.
3. Requests RX/TX waveform, FIFO watermark log, driver ISR trace.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

UART FRAME (8N1)

idle ‾‾‾‾\__ D0 D1 D2 D3 D4 D5 D6 D7 /‾‾‾ idle
         ^start          (LSB first)   ^stop
no shared clock: both sides must agree on baud within ~2-3%

ROOT-CAUSE TREE — UART Flow Control

overrun count, baud mismatch, interrupt service latency looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time